Impact of floating gate dry etching on erase characteristics in NOR flash memory

IEEE Electron Device Letters - Tập 23 Số 8 - Trang 476-478 - 2002
W.H. Lee1, Dong-Kyu Lee1, Young-Ho Na1, Keon-Soo Kim1, Kun-Ok Ahn1, Kang-Deog Suh1, Yonghan Roh2
1NVM Team, Memory Division, Samsung Electronics Limited, South Korea
2School of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea

Tóm tắt

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.

Từ khóa

#Nonvolatile memory #Dry etching #Flash memory #Plasma applications #Plasma properties #Tunneling #Gases #Degradation #Plasma stability #Threshold voltage

Tài liệu tham khảo

10.1109/IEDM.1996.553150 10.1109/16.772476 10.1109/16.293318 10.1109/IEDM.1994.383410 10.1109/IEDM.1994.383367 10.1109/RELPHY.1994.307820 10.1063/1.1657043 10.1109/IEDM.1994.383280 10.1109/55.145056 10.1109/VLSIT.1993.760256