High-speed low-complexity implementation for data weighted averaging algorithm [/spl Sigma//spl Delta/ modulator applications]
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 283-286
Tóm tắt
In this paper, a high-speed, low-complexity implementation of a data weighted averaging (DWA) algorithm is presented. Different from other published implementations, the maximum speed-limited function of the DWA algorithm, decoding for control signal generation and adding for register value updating, are replaced by carry look-ahead and rotating. Additionally, register simplification is adopted to reduce area costs. This design, in 0.25 /spl mu/m CMOS, for a 3-bit 8-element example can operate at a 800 MHz clock rates for post-layout simulations, and costs only 254 transistors.
Từ khóa
#Cities and towns #Decoding #Costs #Delta-sigma modulation #Logic #Circuits #Physics #Data engineering #DH-HEMTs #Signal generatorsTài liệu tham khảo
10.1109/4.597283
10.1109/4.890296
10.1109/82.749090
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