High performance BiCMOS circuit technology VLSI gate arrays

Symposium 1989 on VLSI Circuits - 1989
Gallia1, Yee1, Chau1, Wang1, Davis1, Moore1, Chas, Lemonds1, Eklund1, Havemann1, Bonifield1, Graham1, Pozadzides1, Shah1
1Texas Instruments, Inc., Dallas, TX, USA

Tóm tắt

This paper discusses the design and technology for a high density, full BiCMOS channelless gate array. A gate delay of 360ps lor a 0.4pf load has been achieved on a 106k gate (2- input NAND equivalent) test chip.

Từ khóa

#Logic gates #BiCMOS integrated circuits #Transistors #Delays #Capacitance #Integrated circuit interconnections #Layout

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Symposium 1989 on VLSI Circuits

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