High-accuracy function synthesizer circuit with applications in signal processing
Tóm tắt
An original low-voltage current-mode high-accuracy function synthesizer circuit will be presented, allowing to implement a multitude of continuous mathematical functions. The dynamic range is strongly extended as a result of the superior-order approximation of the implemented functions. The current-mode operation and the independence of the circuit performances on technological parameters are responsible for an additional improvement of structure accuracy. The advantages of reduced design costs per function represent an immediate consequence of the multiple functions realized by the proposed structure. The approximation error of the original function synthesizer circuit is 0.3% for an extended range of the input signal. The function synthesizer is designed for implementing in 0.18 μm CMOS technology and it is supplied at 1 V. An original application of the proposed function synthesizer circuit is represented by a new fourth-order approximation exponential function generator, having a dynamic range of approximately 33 dB, for an error smaller than 1 dB.
Tài liệu tham khảo
Rittenhouse G, Goyal S, Neilson DT, Samuel S: Sustainable telecommunications. Technical Symposium at ITU Telecom World, Geneva, Switzerland; 2011:19-23.
Altiparmak F, Dengiz B, Smith AAE: General neural network model for estimating telecommunications network reliability. IEEE Trans. Reliab. 2009, 58(1):2-9.
Popa C: Superior-Order Curvature-Correction Techniques for Voltage References. Springer, New York; 2009.
Popa C: Synthesis of Computational Structures for Analog Signal Processing. Springer, New York; 2011.
Du Preez CC, Sinha S, du Plessis M: CMOS ECG, EEG and EMG waveform bio-simulator. International Semiconductor Conference 2006, 1: 27-29. September 2006, Sinaia, Romania, pp. 29–38
Pini F, McCarthy K: Capacitive instrumentation amplifier for low-power bio potential signal detection. Paper presented at Signals and Systems Conference, Cork, Ireland; 2010:54-58. 23–24 June 2010
Azzolini C, Ricciardi A, Boi A: Very low-cost CMOS audio amplifier for 1-V portable applications. Paper presented at 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, Tozeur, Tunisia; 2008:25-27. pp. 1–4
C Azzolini, A Boni, A 1-V CMOS audio amplifier for low cost hearing aids, in Paper presented at 15th IEEE International Conference on Electronics, Circuits and Systems, 31 August – 3: St. (Julian's, Malta; September 2008):562-565.
Wei DC, Sun DQ, Abidi AA: A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive read channel. IEEE J. Solid State Circuits 2001, 36(11):1795-1807. 10.1109/4.962303
Ndjountche T, Fa-Long L, Bobda C: A CMOS front-end architecture for hard-disk drive read-channel equalizer. Paper presented at IEEE International Symposium on Circuits and Systems, Kobe, Japan; 2005:2184-2187. vol. 3, 23–26 May
Hwang-Cherng C, Jia-Yu W: High CMRR instrumentation amplifier for biomedical applications. Paper presented at 9th International Symposium on Signal Processing and Its Applications, 12–15 February 2007, Sharjah, United Arab Emirates; 2007:1-4.
Haider MR, Islam SK, Mostafa S, Mo Z, Taeho O: Low-power low-voltage current readout circuit for inductively powered implant system. IEEE Trans. Biomed. Circuits Syst. 2010, 4(4):205-213.
Dlugosz R, Talaska T, Pedrycz W, Wojtyna R: Realization of the conscience mechanism in CMOS implementation of winner-takes-all self-organizing neural networks. IEEE Trans. Neural Netw. 2010, 21(6):961-971.
Ebong IE, Mazumder P: CMOS and memristor-based neural network design for position detection. Proc. IEEE 2011, 99: 1-11.
Ming-Dou K: ESD-aware circuit design in CMOS integrated circuits to meet system-level ESD specification in microelectronic systems. Paper presented at International Conference of Electron Devices and Solid-State Circuits, Tianjin, China; 2011:1-2. 17–18 November 2011
Seung-Chul L, Young-Deuk J, Jong-Kee K, Jongdae K: A 10-bit 205-MS/s 1.0-mm2 90-nm CMOS pipeline ADC for flat panel display applications. IEEE J. Solid State Circuits 2007, 42(12):2688-2695.
Sudha N, Sridharan K: A high-speed VLSI design and ASIC implementation for constructing Euclidean distance-based discrete Voronoi diagram. IEEE Trans. Robot. Autom. 2004, 20(2):352-358. 10.1109/TRA.2004.824638
Villmann T, Schleif FM, Hammer B: Fuzzy Labeled Soft Nearest Neighbor Classification with Relevance Learning. Paper presented at Fourth International Conference on Machine Learning and Applications, Los Angeles, USA; 2005:11-15. 15–17 December 2005
Triguero I, Derrac J, Garcia S, Herrera F: A taxonomy and experimental study on prototype generation for nearest neighbor classification. IEEE Trans. Syst. Man Cybern. C: Appl. Rev. 2012, 42(1):86-100.
Rodríguez-Vázquez A, Domínguez-Castro R, Jiménez-Garrido F, Morillas S, García-Ortiz A, Utrera C, Pardo MD, Listan J, Romay R: Cellular Nanoscale Sensory Wave Computing—A CMOS Vision System On-Chip with Multi-Core, Cellular Sensory-Processing Front-End. Edited by: Baatar C, Porod W, Roska T. Springer, New York; 2010:129-146.
Sawigun C, Mahattanakul J: A 1.5 V, wide-input range, high-bandwidth, CMOS four-quadrant analog multiplier. IEEE International Symposium on Circuits and Systems, Washington, USA; 2008:2318-2321. 18–21 May 2008
Akshatha BC, Akshintala VK: Low voltage, low power, high linearity, high speed CMOS voltage mode analog multiplier. Paper presented at 2nd International Conference on Emerging Trends in Engineering and Technology, Nagpur, India; 2009:149-154. 16–18 December 2009
Mahmoud SA: Low voltage low power wide range fully differential CMOS four-quadrant analog multiplier. Paper presented at 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, Mexico; 2009:130-133. 2–5 August 2009
Naderi A, Khoei A, Hadidi K: High speed, low power four-quadrant CMOS current-mode multiplier. Paper presented at 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco; 2007:1311. 11–14 December 2007
Gravati M, Valle M, Ferri G, Guerrini N, Reyes N: A novel current-mode very low power analog CMOS four quadrant multiplier. Paper presented at 31st European Solid-State Circuits Conference, Grenoble, France; 2005:495-498. 12–16 September 2005
Sawigun C, Serdijn WA: Ultra-low-power, class-AB. CMOS four-quadrant current multiplier. Electron. Lett. 2009, 45(10):483-484.
Hidayat R, Dejhan K, Moungnoul P, Miyanaga Y: OTA-based high frequency CMOS multiplier and squaring circuit. Paper presented at International Symposium on Intelligent Signal Processing and Communications Systems, Bangkok, Thailand; 2009:1-4. 8–10 Ferbruary 2009
Machowski W, Kuta S, Jasielski J, Kolodziejski W: Quarter-square analog four-quadrant multiplier based on CMOS invertes and using low voltage high speed control circuits. Paper presented at 17th International Conference Mixed Design of Integrated Circuits and Systems, Wroclaw, Poland; 2010:333-336. 24–26 June 2010
Ehsanpour M, Moallem P, Vafaei A: Design of a novel reversible multiplier circuit using modified full adde. Paper presented at International Conference on Computer Design and Applications, Qinhuangdao, China; 2010:V3-230-V3-234. vol. 3, 25–27 June 2010
Naderi A, Mojarrad H, Ghasemzadeh H, Khoei A, Hadidi K: Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed. IEEE International Conference on “Computer As A Tool, Saint Petersburg, Russia; 2009:282-287. 18–23 May 2009
Kao CH, Tseng CC, Hsieh CS: Low-voltage exponential function converter. IEE Proc. Circuits Dev. Syst. 2005, 152(5):485-487. 10.1049/ip-cds:20045110
Ethier S, Sawan M: Exponential Current pulse generation for efficient very high-impedance multisite stimulation. IEEE Trans. Biomed. Circuits Syst 2010, 99: 1-9.
Hedayati H, Bakkaloglu B: A 3 GHz wideband ∑Δ fractional-N synthesizer with voltage-mode exponential CP-PFD. Paper presented at IEEE Radio Frequency Integrated Circuits Symposium, Boston, USA; 2009:325-328. 7–9 June 2009
Moro-Frias D, Sanz-Pascual MT, de la Cruz-Bias CA: Linear-in-dB Variable Gain Amplifier with PWL exponential gain control. Paper presented at IEEE International Symposium on Circuits and Systems, Paris, France; 2010:2824-2827. 2010
CA De La Cruz Blas, O Feely, Limit cycle behavior in a class-AB second-order square root domain filter, in Paper presented at 15th IEEE International Conference on Electronics, Circuits and Systems, 31 August – 3: St. (Julian's, Malta; September 2008):117-120.
Boonchu B, Surakampontom W: A CMOS current-mode squarer/rectifier circuit. Paper presented at International Symposium on Circuits and Systems, Bangkok, Thailand; 2003:I-405-I-408. vol. 1, 25–28 May 2003
CA De La Blas, A Lopez, A novel two quadrant MOS translinear Squarer-divider cell, in Paper presented at 15th IEEE International Conference on Electronics, Circuits and Systems, 31 August – 3 Sptember: St. (Julian's, Malta; 2008):5-8.
De La Cruz-Blas CA, Lopez-Martin AJ, Carlosena A: 1.5-V square-root domain second-order filter with on-chip tuning. IEEE Trans. Circuits Syst. I: Regular Papers 2005, 52(10):1996-2006.
Raikos G, Vlassis S: Low-voltage CMOS voltage squarer. Paper presented at 16th IEEE International Conference on Electronics, Circuits, and Systems, Yasmine Hammamet, Tunisia; 2009:159-162. 13–16 December 2009
Garofalo V, Coppola M, De Caro D, Napoli E, Petra N, Strollo AGM: A novel truncated squarer with linear compensation function. Paper presented at IEEE International Symposium on Circuits and Systems, Paris, France; 2010:4157-4160. 30 May – 2 June 2010
Kircay A, Keserlioglu MS: Novel current-mode second-order square-root-domain highpass and allpass filter. Paper presented at International Conference on Electrical and Electronics Engineering, Bursa, Turkey; 2009:242-246. 5–8 November 2009
Popa C: A New FGMOST Euclidean Distance Computational Circuits Based on Algebraic Mean of the Input Potentials. Springer, Berlin; 2009:459-466. Lecture Notes in Computer Science
Hyo-Jin A, Chang-Seok C, Hanho L: High-speed low-complexity Folded Degree-Computationless Modified Euclidean algorithm architecture for RS decoders. Paper presented at 12th International Symposium on Integrated Circuits, Singapore, Singapore; 2009:582-585. 14–16 December 2009
Abuelma’atti MT, Al-Yahia NM: An improved universal CMOS current-mode analog function synthesizer. Paper presented at International Symposium on Integrated Circuits, Singapore; 2007:580-583. 26–30 September 2007
Abuelma’atti MT: Universal CMOS current-mode analog function synthesizer. IEEE Trans. Circuits Syst. I: Fund. Theory Appl 2002, 49(10):1468-1474. 10.1109/TCSI.2002.803356
Abuelma’atti MT: A translinear current-mode programmable analog exponential function synthesizer. Paper presented at Eleventh International Conference on Microelectronics, Kuwait; 1999:209-212. 22–24 November 1999
Psychalinos C, Vlassis S: A systematic design procedure for square-root-domain circuits based on the signal flow graph approach. IEEE Trans. Circuits Syst. I: Fund. Theory Appl. 2002, 49(12):1702-1712. 10.1109/TCSI.2002.805695
Baker GA, Graves-Morris P: Padé Approximants (Cambridge University Press. Cambridge, MA; 1996.