Chi On Chui1, S. Ramanathan2, B.B. Triplett2, P.C. McIntyre2, K.C. Saraswat1
1Department of Electrical Engineering, University of Stanford, Stanford, CA, USA
2Department of Materials Science and Engineering, University of Stanford, Stanford, CA, USA
Tóm tắt
For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity (/spl kappa/) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410/spl deg/C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO/sub 2/ thickness (EOT) on the order of 5-8 /spl Aring/ and capacitance-voltage (C-V) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.