FIR filter optimization for video processing on FPGAs
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Bovik A: The Essential Guide to Image Processing. Academic Press, Waltham; 2009.
Kumm M, Zipf P: Hybrid multiple constant multiplication for FPGAs. In International Conference on Electronics, Circuits and Systems (ICECS). IEEE Piscataway; 2012:556-559.
Bull DR, Horrocks DH: Primitive operator digital filters. IEEE Proc. Circuits, Devices Syst 1991, 138(3):401-412. 10.1049/ip-g-2.1991.0066
Voronenko Y, Püschel M: Multiplierless multiple constant multiplication. ACM Trans. Algorithms (TALG) 2007, 3(2):1-38.
Meyer-Baese U, Chen J, Chang CH, Dempster AG: A comparison of pipelined RAG-n and DA FPGA-based multiplierless filters. In Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE Piscataway; 2006:1555-1558.
Mirzaei S, Kastner R, Hosangadi A: Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs. Int. J Reconfigurable Comput 2010, 3: 1-17.
Meyer-Baese U, Botella G, Romero D, Kumm M: Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm. In SPIE Defense Security+Sensing, Volume 8401. SPIE Baltimore; 2012:1-12.
Kumm M, Zipf P: High speed low complexity FPGA-based FIR filters using pipelined adder graphs. In International Conference on Field Programmable Technology (ICFPT). IEEE Piscataway; 2011:1-4.
Kumm M, Faust M, Zipf P, Chang CH: Pipelined adder graph optimization for high speed multiple constant multiplication. In International Symposium on Circuits and Systems (ISCAS). IEEE Piscataway; 2012:49-52A.
Kumm M, Liebisch K, Zipf P: Reduced Complexity Single and Multiple constant multiplication in Floating point precision. In International Conference on Field Programmable Logic and Applications (FPL). IEEE Piscataway; 2012:255-261.
Hartley R: Subexpression sharing in filters using canonic signed digit multipliers. IEEE Trans. Circuits and Syst. II: Analog Digit. Signal Process 1996, 43(10):677-688. 10.1109/82.539000
Mirzaei S, Hosangadi A, Kastner R: FPGA implementation of high speed FIR filters using add and shift method. In International Conference on Computer Design (ICCD). IEEE Piscataway; 2006:308-313.
Imran M, Khursheed K, O’Nils M: On the number representation in sub-expression sharing. In International Conference on Signals and Electronic Systems (ICSES). IEEE Piscataway; 2010:17-20.
Dempster AG, Macleod MD: Constant integer multiplication using minimum adders. IEE Proc. Circuits, Devices Syst 1994, 141(5):407-413. 10.1049/ip-cds:19941191
Dempster AG, Macleod MD: Use of minimum-adder multiplier blocks in FIR digital filters. IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process 1995, 42(9):569-577. 10.1109/82.466647
Gustafsson O: A difference based adder graph heuristic for multiple constant multiplication problems. In International Symposium on Circuits and Systems (ISCAS). IEEE Piscataway; 2007:1097-1100.
Aksoy L, Günes E, Flores P: Search algorithms for the multiple constant multiplications problem: exact and approximate. Microprocessors and Microsystems 2010, 34(5):151-162. 10.1016/j.micpro.2009.10.001
Flores P, Monteiro J, Costa E: An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE Computer Society Washington; 2005:13-16.
Yurdakul A, Dündar G: Multiplierless realization of linear DSP transforms by using common two-term expressions. J. VLSI Signal Process 1999, 22: 163-172. 10.1023/A:1008125221674
Aksoy L, Costa E, Flores P, Monteiro J: Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. In 43rd ACM/IEEE Design Automation Conference (DAC). IEEE Piscataway; 2006:669-674.
Aksoy L, Costa E, Flores P, Monteiro J: Optimization of Area in Digital FIR Filters Using Gate-Level Metrics. In 44th ACM/IEEE Design Automation Conference (DAC). IEEE; 2007:420-423.
Aksoy L, da Costa E, Flores P, Monteiro J: Exact and approximate algorithms for the optimization of area and delay in multiple constant multiplications. IEEE Trans. Computer-Aided Design Integrated Circuits Syst 2008, 27(6):1013-1026.
Aksoy L, Gunes E, Flores P: An Exact Breadth-First Search Algorithm for the Multiple Constant Multiplications Problem. In NORCHIP. IEEE Piscataway; 2008:41-46.
Gustafsson O: Towards optimal multiple constant multiplication: a hypergraph approach. In 42nd Asilomar Conference on Signals, Systems and Computers. IEEE Piscataway; 2008:1805-1809.
Gustafsson O: Lower bounds for constant multiplication problems. IEEE Trans. Circuits Syst. II: Express Briefs 2007, 54(11):974-978.
Aksoy L, Costa E, Flores P, Monteiro J: Design of low-power multiple constant multiplications using low-complexity minimum depth operations. In Proceedings of the 21st Edition of the Great Lakes Symposium on VLSI. ACM New York; 2011:79-84.
Dempster A, Dimirsoy S, Kale I: Designing multiplier blocks with low logic depth. In International Symposium on Circuits and Systems (ISCAS). IEEE Piscataway; 2002:773-776.
Johansson K, Power Low: Low Power and Low Complexity Shift-and-Add Based Computations. PhD thesis, Linköping University, Department of Electrical Engineering, 2008
Faust M, Chang CH: Minimal logic depth adder tree optimization for multiple constant multiplication. In International Symposium on Circuits and Systems (ISCAS). IEEE Piscataway; 2010:457-460.
Kang HJ, Park IC: FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. IEEE Trans. Circuits Syst. II: Analog Digital Signal Process 2001, 48(8):770-777. 10.1109/82.959867
Aksoy L, Costa E, Flores P, Monteiro J: Optimization of gate-level area in high throughput multiple constant multiplications. In European Conference on Circuit Theory and Design (ECCTD). IEEE Piscataway; 2011:609-612.
Gustafsson O, Dempster A: On the use of multiple constant multiplication in polyphase FIR filters and filter banks. 2004.
Aksoy L, Costa E, Flores P, Monteiro J: Design of low-complexity digital finite impulse response filters on FPGAs. 2012.
Wirthlin M: Constant coefficient multiplication using look-up tables. J. VLSI Signal Process 2004, 36: 7-15.
Faust M, Chang CH: Bit-parallel multiple constant multiplication using look-up tables on FPGA. In International Symposium on Circuits and Systems (ISCAS). IEEE Piscataway; 2011:657-660.
Crosisier A, Esteban DJ, Levilio ME, Riso V: Digital filter for PCM encoded signals. US Patent No. 3777130 (1973)
Zohar S: New hardware realizations of nonrecursive digital filters. IEEE Trans. Comput 1973, 22(4):328-338.
Peled A, Liu B: A new hardware realization of digital filters. IEEE Trans. Acoustics, Speech Signal Process 1974, 22(6):456-462. 10.1109/TASSP.1974.1162619
White SA: Applications of distributed arithmetic to digital signal processing: a tutorial review. IEEE ASSP Mag 1989, 6(3):4-19.
Sen W, Bin T, Jim Z: Distributed arithmetic for FIR filter design on FPGA. In International Conference on Communications, Circuits and Systems (ICCCAS). IEEE Piscataway; 2007:620-623.
Meher P, Chandrasekaran S, Amira A: FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans. Signal Process 2008, 56(7):3009-3017.
Kumm M, Möller K, Zipf P: Reconfigurable FIR filter using distributed arithmetic on FPGAs. In International Symposium on Circuits and Systems (ISCAS). IEEE Piscataway; (accepted for publication in 2013)
Willson A: Desensitized half-band filters. IEEE Trans. Circuits and Syst I: Regular Papers 2010, 57: 152-167.
Lu WS, Wang HP, Antoniou A: Design of two-dimensional FIR digital filters by using the singular-value decomposition. IEEE Trans. Circuits and Syst 1990, 37: 35-4. 10.1109/31.45689
IBM Inc: IBM ILOG CPLEX Optimizer. . Accessed 16 April 2013 http://www.ilog.com/products/cplex
IBM Inc: IBM ILOG CPLEX V12.1 - File Formats Supported by CPLEX (2009).
Lavin C, Padilla M, Lamprecht J, Lundrigan P, Nelson B, Hutchings B: RapidSmith: do-it-yourself CAD tools for Xilinx FPGAs. In International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2011:349-355.
Simkins JM, Philofsky BD: Structures and methods for implementing ternary adders/subtractors in programmable logic devices. US Patent No 7274211, Xilinx Inc. (2006)
Baeckler G, Langhammer M, Schleicher J, Yuan R: Logic cell supporting addition of three binary words. US Patent No 7565388, Altera Coop. (2009)