Encapsulation of 1-Up fpBGA from design to production

The plastic near chip scale ball grid array (fpBGA) package has already begun to take over certain segments of the surface mount technology (SMT) industry, and its hold on the market is expected to continue growing over the next few years. A fpBGA in general, offers a smaller footprint than a QFP package with similar pin count. In addition, fpBGA significantly reduces the risk of component handling damage, reduces power supply noise and offers the same or better performance than leaded packages. With the ever-increasing demand for high density, high I/O count packaging, fpBGA is fast becoming the next generation package. fpBGA package is a method of reducing package size and its pin-to-pin trace gap in order to integrate more functions and reliability in a single space. Conventional encapsulation methodology for fpBGA is by panel molding, normally into multiple (4 or 5) sections. This reduces the substrate material utilization. In this paper design methodology and package reliability for a 1-up (I section) fpBGA will be presented. Reliability consideration includes JEDEC package reliability standard. Package reliability data will be discussed. Package co-planarity data will be compared. The encapsulation results to be discussed will include EMC selection criteria, PMC techniques to control warpage, and the cause of kinked wire and its control methodology.