Design and optimization of asymmetrical TFET using meta-heuristic algorithms
Tóm tắt
The complex process of semiconductor device design requires precise models and efficient optimizers. This article puts forward an Asymmetrical Hetero-Dielectric (AHD) Triple Material Gate (TMG) n-type Junctionless Tunnel Field Effect Transistor (JL-TFET). A higher gate control is achieved by using triple material in control gate and hetero-dielectric oxide, which results in high ON current and low leakage. The surface potential based model for the proposed structure is derived by analytically solving 2-D Poisson’s equation with hetero-dielectric gate oxide. This work also adopts intelligent techniques for extraction of optimal model parameters by using the derived mathematical model for the proposed JLTFET structure. The optimization technique used in this work combines the advantage of Particle Swarm Optimization (PSO) algorithm and Differential Evolution (DE) algorithm. A comparison with the conventional design process reflects that the use of optimization technique provides a novel approach to tune the process parameters. This technique outperforms the state of art design techniques and provides best accuracy along with exceptional computational efficiency. A current ratio of 1.25 × 1010 A and Point Subthreshold Swing (SS) values of 9 mV/dec and average SS of 48 mV/dec is achieved by optimizing the proposed structure.
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