Design and implementation of high-speed Reed-Solomon decoder
ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605) - Trang 146-149
Tóm tắt
This paper presents a new VLSI design and implementation of a high-speed three-stage pipelining Reed-Solomon decoder based on the modified Euclidean algorithm. A new multiplier and inversion for GF(2/sup m/) are implemented on the composite field GF(2/sup 2n/) (m=2n), which offers lower hardware requirements compared to standard Mastrovito multiplier and ROM respectively. By setting the new initial conditions of MEA, not only decoding latency but also hardware overheads of RS (204,188) decoder is reduced greatly compared to the conventional architecture with the same decoding rate. The complexity of the proposed RS decoder is about 118,000 gates, and the decoding latency is only 220 clock cycles and has a throughput of 800 Mbit/s using 0.25 /spl mu/m CMOS process.
Từ khóa
#Reed-Solomon codes #Decoding #Hardware #Delay #Very large scale integration #Algorithm design and analysis #Pipeline processing #Read only memory #Clocks #ThroughputTài liệu tham khảo
jeng, 1999, A high efficient multiplier for RS decoder, 1999 Int Symp VLSI Technology Systems and Applications, 116
10.1109/12.508323
song, 2000, An efficient architecture for implementing the modified Euclidean algorithm, 9th NASA Symposium on VLSI Design 2000, 4.1.1
lee, 2000, VLSI design of Reed-Solomon decoder architectures, ISCAS2000, 705v
10.1109/12.559805
10.1109/CICC.1990.124728
10.1109/TC.1985.1676579