Design and implementation of an acoustic echo canceller
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 299-302
Tóm tắt
In this paper the AEC (acoustic echo canceller) is designed and implemented using VHDL. The designed echo canceller employs a pipeline and master-slave structure, and is realized with FPGA. As an adaptive algorithm, the normalized LMS algorithm is used. For coefficient adjustment, the stochastic iteration algorithm (SIA) which uses only current residual values is used and the number of registers are evidently reduced and convergence speed is also much improved compared to existing methods by using an embedded array block of FPGA for the FIR filter structure of the transceiver. The designed echo canceller is verified with the test board implemented for this paper. With the top-down design and synthesis using VHDL, the design time is reduced and modular design is achieved.
Từ khóa
#Echo cancellers #Field programmable gate arrays #Pipelines #Master-slave #Adaptive algorithm #Least squares approximation #Stochastic processes #Convergence #Finite impulse response filter #TransceiversTài liệu tham khảo
1994, Digital Voice Echo Canceller Implementation on the TMS320C5x, Telecommunications Applications with the TMS320C5x DSPs, Literature number SPRAG33, 189
1997, Implementing a Li ne-Echo Canceller on the TMS320C54X, Telecommunications Applications, Literature number SPRA188, 2
rubinfield, 1975, a proof of the modified booth's algorithm for multiplication, IEEE Transactions on Computers, c 24, 1014, 10.1109/T-C.1975.224114
ting, 2000, High-Performance Fine-Grained Pipelined LMS Algorithm In Virtex FPGA, Proceedings of SPIE Advanced Signal Processing Algorithms Architectures and Implementations, 4116
2001, FLEX 10K Embedded Programmable Logic Device Family Data Sheet, Altera
10.1109/82.539001
farhang-boroujeny, 1998, Adaptive Filters Theory and Applications
haykin, 2002, Adaptive Filter Theory