DCT processor architecture based on computation sharing
ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605) - Trang 162-165
Tóm tắt
In this paper, we present a new discrete cosine transform (DCT) processor architecture using computation sharing multiplication (CSHM). We introduce a computation sharing multiplier based DCT architecture to achieve image quality and hardware complexity trade-off and analyze the performance. Comparison of the performance, area and power consumption with a DA (distributed arithmetic) based DCT architecture is performed. The result shows that the proposed architecture improves power consumption by 14% and area by 41% with acceptable image quality degradation.
Từ khóa
#Discrete cosine transforms #Computer architecture #Image quality #Signal processing algorithms #Energy consumption #Image coding #Matrix decomposition #Power engineering computing #Computational Intelligence Society #HardwareTài liệu tham khảo
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