Circuit design of a 9ns-HIT-delay 32K byte cache macro

After a Reduced Instruction Set Computer (RISC) was shown to be effective in increasing CPU performance, several attempts have teen made to further improve the CPU performance by including cache memory an the same chipl21. However, the formerly reported cache size is limited up to 2K bytes. which is not sufficient to obtain more than 95% hit rate. This paper describes a 32K byte cache macro with an experimental RISC implemented on the Same chip.