CMOS subnanosecond true-ECL output buffer

Seevinck1, Dikken1, Schumacher1
1Philips Research Laboratory, Eindhoven, Netherlands

Tóm tắt

This paper presents, for the first time, a CMOS output buffer circuit compatible with standard ECL lOOk systems and not needing external components or additional supply voltages. High speed (0.9 ns delay), sufficient precision and good pulse-response are achieved through use of a new circuit principle. The circuit has been fabricated in an 0.7 μm memory process.

Từ khóa

#Transistors #Delays #Capacitance #Logic gates #Circuit stability #Voltage measurement #Transmission line measurements

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