Barnat, J., Brim, L., Češka, M., Ročkai, P.”: DiVinE: parallel distributed model checker (tool paper). In: Proceedings of Parallel and Distributed Methods in Verification and High Performance Computational Systems Biology HiBi/PDMC 2010 (Twente, The Netherlands), pp. 4–7. IEEE Computer Society Press, Sept 2010
Belinfante, A., Feenstra, J., de Vries, R.G., Tretmans, J., Goga, N., Feijs, L., Mauw, S., Heerink, L.: Formal test automation: a simple experiment. In: Proceedings of the IFIP 12th International Workshop on Testing of Communicating Systems IWTCS’99 (Budapest, Hungary). Kluwer, Dordrecht, Sept 1999
Bergamini, D., Descoubes, N., Joubert, C., Mateescu, R.: BISIMULATOR: a modular tool for on-the-fly equivalence checking. In: Proceedings of the 11th International Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS’2005 (Edinburgh, Scotland, UK). Lecture Notes in Computer Science, vol. 3440, pp. 581–585. Springer, Berlin, April 2005
Berthomieu, B., Bodeveix, J.-P., Farail, P., Filali, M., Garavel, H., Gaufillet, P., Lang, F., Vernadat, F.: FIACRE: An intermediate language for model verification in the TOPCASED environment. In: Proceedings of the 4th European Congress on Embedded Real-Time Software ERTS’08 (Toulouse, France). SIA (the French Society of Automobile Engineers), AAAF (the French Society of Aeronautic and Aerospace), and SEE (the French Society for Electricity, Electronics, and Information & Communication Technologies), Jan 2008
Blom, S., van de Pol, J., Weber, M.: LTSmin: distributed and symbolic reachability. In: Proceedings of the 22nd International Conference on Computer Aided Verification CAV 2010 (Edinburgh, UK). Lecture Notes in Computer Science, vol. 6174, pp. 354–359. Springer, Berlin, July 2010
Bouajjani, A., Fernandez, J.-C., Graf, S., Rodríguez, C., Sifakis, J.: Safety for branching time semantics. In: Proceedings of 18th ICALP. Springer, Berlin, July 1991
Bouali, A., Ressouche, A., Roy, V., de Simone, R.: The Fc2Tools set: a toolset for the verification of concurrent systems. In: Proceedings of the 8th Conference on Computer-Aided Verification (New Brunswick, New Jersey, USA). Lecture Notes in Computer Science, vol. 1102. Springer, Berlin, Aug 1996
Boyer, F., Gruber, O., Salaün, G.: Specifying and verifying the SYNERGY reconfiguration protocol with LOTOS NT/CADP. In: Proceedings of the 17th International Symposium on Formal Methods FM’2011 (Limerick, Ireland). Lecture Notes in Computer Science, vol. 6664, pp. 103–117. Springer, Berlin, June 2011
Bozga, M., Fernandez, J.-C., Ghirvu, L., Graf, S., Krimm, J.-P., Mounier, L.: IF: an intermediate representation and validation environment for timed asynchronous systems. In: Proceedings of World Congress on Formal Methods in the Development of Computing Systems FM’99 (Toulouse, France). Springer, Berlin, Sept 1999
Champelovier, D., Clerc, X., Garavel, H., Guerte, Y., McKinty, C., Powazny, V., Lang, F., Serwe, W., Smeding, G.: Reference Manual of the LOTOS NT to LOTOS Translator (Version 5.4). INRIA/VASY, Sept 2011
Chehaibar, G., Garavel, H., Mounier, L., Tawbi, N., Zulian, F.: Specification and verification of the powerscale bus arbitration protocol: an industrial experiment with LOTOS. In: Proceedings of the Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols, and Protocol Specification, Testing, and Verification FORTE/PSTV’96 (Kaiserslautern, Germany), pp. 435–450. IFIP, Chapman & Hall, Oct 1996. Full version available as INRIA Research Report RR-2958
Chossart, R.: Évaluation d’outils de vérification pour les spécifications de systèmes d’information. Mémoire maître ès sciences, Université de Sherbrooke, Canada, Mar 2010
Cleaveland, R., Li, T., Sims, S.: The Concurrency Workbench of the New Century (Version 1.2). User’s manual, July 2000
Cleaveland, R., Parrow, J., Steffen, B.: The Concurrency Workbench. In: Proceedings of the 1st Workshop on Automatic Verification Methods for Finite State Systems (Grenoble, France). Lecture Notes in Computer Science, vol. 407, pp. 24–37. Springer, Berlin, June 1989
Cornejo, M.A., Garavel, H., Mateescu, R., de Palma, N.: Specification and verification of a dynamic reconfiguration protocol for agent-based applications. In: Proceedings of the 3rd IFIP WG 6.1 International Working Conference on Distributed Applications and Interoperable Systems DAIS’2001 (Krakow, Poland), pp. 229–242. IFIP, Kluwer, Dordrecht, Sept 2001. Full version available as INRIA Research Report RR-4222
Coste, N., Garavel, H., Hermanns, H., Lang, F., Mateescu, R., Serwe, W.: Ten years of performance evaluation for concurrent systems using CADP. In: Proceedings of the 4th International Symposium on Leveraging Applications of Formal Methods, Verification and Validation ISoLA 2010 (Amirandes, Heraclion, Crete), Part II. Lecture Notes in Computer Science, vol. 6416, pp. 128–142. Springer, Berlin, Oct 2010
Coste, N., Hermanns, H., Lantreibecq, E., Serwe, W.: Towards performance prediction of compositional models in industrial GALS designs. In: Proceedings of the 21th International Conference on Computer Aided Verification CAV’2009 (Grenoble, France). Lecture Notes in Computer Science, vol. 5643, pp. 204–218. Springer, Berlin, July 2009
Crouzen, P., Lang, F.: Smart reduction. In: Proceedings of Fundamental Approaches to Software Engineering FASE’2011 (Saarbrücken, Germany). Lecture Notes in Computer Science, vol. 6603, pp. 111–126. Springer, Berlin, Mar 2011
Emerson, E.A., Lei, C.-L.: Efficient model checking in fragments of the propositional Mu-calculus. In: Proceedings of the 1st International Symposium on Logic in Computer Science LICS’86, pp. 267–278 (1986)
Fernandez, J.-C.: ALDEBARAN: un système de vérification par réduction de processus communicants. Thèse de Doctorat, Université Joseph Fourier (Grenoble), May 1988
Fernandez, J.-C., Garavel, H., Kerbrat, A., Mateescu, R., Mounier, L., Sighireanu, M.: CADP (CÆSAR/ALDEBARAN Development Package): A Protocol Validation and Verification Toolbox. In: Proceedings of the 8th Conference on Computer-Aided Verification (New Brunswick, New Jersey, USA). Lecture Notes in Computer Science, vol. 1102, pp. 437–440. Springer, Berlin, Aug 1996
Fernandez, J.-C., Garavel, H., Mounier, L., Rasse, A., Rodríguez, C., Sifakis, J.: A toolbox for the verification of LOTOS programs. In: Proceedings of the 14th International Conference on Software Engineering ICSE’14 (Melbourne, Australia), pp. 246–259. ACM, New York, May 1992
Fernandez, J.-C., Richier, J.-L., Voiron, J.: Verification of protocol specifications using the CESAR system. In: Proceedings of the 5th IFIP International Workshop on Protocol Specification, Testing and Verification (Moissac, France), pp. 71–90. IFIP, North-Holland, June 1985
Garavel, H.: Compilation et vérification de programmes LOTOS. Thèse de Doctorat, Université Joseph Fourier (Grenoble), Nov 1989
Garavel, H.: On the introduction of gate typing in E-LOTOS. Rapport SPECTRE 94-3, VERIMAG, Grenoble, Feb. 1994. Annex D of ISO/IEC JTC1/SC21/WG1 N1314 Revised Draft on Enhancements to LOTOS and Annex C of ISO/IEC JTC1/SC21/WG1 N1349 Working Draft on Enhancements to LOTOS
Garavel, H.: Défense et illustration des algèbres de processus. In Actes de l’Ecole d’été Temps Réel ETR 2003 (Toulouse, France). Institut de Recherche en Informatique de Toulouse, Sept 2003
Garavel, H., Helmstetter, C., Ponsini, O., Serwe, W.: Verification of an industrial SystemC/TLM model using LOTOS and CADP. In: Proceedings of the 7th ACM-IEEE International Conference on Formal Methods and Models for Codesign MEMOCODE’2009 (Cambridge, MA, USA). IEEE Computer Society Press, June 2009
Garavel, H., Lang, F., Mateescu, R., Serwe, W.: CADP 2006: A toolbox for the construction and analysis of distributed processes. In: Proceedings of the 19th International Conference on Computer Aided Verification CAV’2007 (Berlin, Germany). Lecture Notes in Computer Science, vol. 4590, pp. 158–163. Springer, Berlin, July 2007
Garavel, H., Lang, F., Mateescu, R., Serwe, W.: CADP 2010: a toolbox for the construction and analysis of distributed processes. In: Proceedings of the 17th International Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS’2011 (Saarbrücken, Germany). Lecture Notes in Computer Science, vol. 6605, pp. 372–387. Springer, Berlin, Mar 2011
Garavel, H., Mateescu, R., Bergamini, D., Curic, A., Descoubes, N., Joubert, C., Smarandache-Sturm, I., Stragier, G.: DISTRIBUTOR and BCG_MERGE: tools for distributed explicit state space generation. In: Proceedings of the 12th International Conference on Tools and Algorithms for the Construction and Analysis of Systems TACAS’2006 (Vienna, Austria). Lecture Notes in Computer Science, vol. 3920, pp. 445–449. Springer, Berlin, Mar–Apr 2006
Garavel, H., Mateescu, R., Smarandache, I.: Parallel state space construction for model-checking. In: Proceedings of the 8th International SPIN Workshop on Model Checking of Software SPIN’2001 (Toronto, Canada). Lecture Notes in Computer Science, vol. 2057, pp. 217–234. Springer, Berlin, May 2001. Revised version available as INRIA Research Report RR-4341, Dec 2001
Garavel, H., Sighireanu, M.: Towards a second generation of formal description techniques—rationale for the design of E-LOTOS. In: Proceedings of the 3rd International Workshop on Formal Methods for Industrial Critical Systems FMICS’98 (Amsterdam, The Netherlands), pp. 187–230, Amsterdam, May 1998. CWI. Invited lecture
Garavel, H., Sighireanu, M.: A graphical parallel composition operator for process algebras. In: Proceedings of the Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols, and Protocol Specification, Testing, and Verification FORTE/PSTV’99 (Beijing, China), pp. 185–202. IFIP, Kluwer, Dordrecht, Oct 1999
Garavel, H., Turlier, P.: CÆSAR.ADT: un compilateur pour les types abstraits algébriques du langage LOTOS. In: Actes du Colloque Francophone pour l’Ingénierie des Protocoles CFIP’93 (Montréal, Canada) (1993)
Graf, S., Richier, J.-L., Rodríguez, C., Voiron, J.: What are the limits of model checking methods for the verification of real life protocols? In: Proceedings of the 1st Workshop on Automatic Verification Methods for Finite State Systems (Grenoble, France). Lecture Notes in Computer Science, vol. 407, pp. 275–285. Springer, Berlin, June 1989
Groote, J.F., Ponse, A.: The syntax and semantics of μCRL. In: Algebra of Communicating Processes’94, Workshops in Computing Series, pp. 26–62. Springer, Berlin (1995)
Helmstetter, C.: TLM.OPEN: a SystemC/TLM Front-End for the CADP Verification Toolbox. Workshop on Simulation Based Development of Certified Embedded Systems SBDCES’09 (Awaji Island, Hyogo, Japan), Oct 2009
Hermanns H.: Interactive Markov Chains and the Quest for Quantified Quality. Lecture Notes in Computer Science, vol. 2428. Springer, Berlin (2002)
Holzmann G.J.: The SPIN Model Checker: Primer and Reference Manual. Addison-Wesley, Reading (2003)
ISO/IEC.: LOTOS—a formal description technique based on the temporal ordering of observational behaviour. International Standard 8807, International Organization for Standardization—Information Processing Systems—Open Systems Interconnection, Genève, Sept 1989
ISO/IEC. Enhancements to LOTOS (E-LOTOS). International Standard 15437:2001, International Organization for Standardization—Information Technology, Genève, Sept 2001
ITU-T.: Specification and Description Language (SDL). ITU-T Recommendation Z.100. International Telecommunication Union, Genève (1992)
Khan, A.M.: Connection of Compositional Verification Tools for Embedded Systems. Mémoire master 2 recherche, Université Joseph Fourier, Grenoble, June 2006
Liu, X., Smolka, S.A.: Simple linear-time algorithms for minimal fixed points. In: Proceedings of the 25th International Colloquium on Automata, Languages, and Programming ICALP’98 (Aalborg, Denmark). Lecture Notes in Computer Science, vol. 1443, pp. 53–66. Springer, Berlin, July 1998
Magee, J., Kramer, J.: Concurrency: State Models and Java Programs. Wiley, New York (2006)
Malhotra, J., Smolka, S.A., Giacalone, A., Shapiro, R.: A tool for hierarchical design and simulation of concurrent systems. In: Proceedings of the BCS-FACS Workshop on Specification and Verification of Concurrent Systems (Stirling, Scotland), pp. 140–152, Swindon, UK. British Computer Society, July 1988
Mateescu, R.: Vérification des propriétés temporelles des programmes parallèles. Thèse de Doctorat, Institut National Polytechnique de Grenoble, April 1998
Mateescu, R., Garavel, H.: XTL: a meta-language and tool for temporal logic model-checking. In: Proceedings of the International Workshop on Software Tools for Technology Transfer STTT’98 (Aalborg, Denmark), pp. 33–42. BRICS, July 1998
Mateescu, R., Serwe, W.: Model checking and performance evaluation with CADP illustrated on shared-memory mutual exclusion protocols. Sci. Comput. Program. (2012). doi:10.1016/j.scico.2012.01.003
Milner R.: Communication and Concurrency. Prentice-Hall, Englewood Cliffs (1989)
Queille J.-P.: Le système CESAR: description, spécification et analyse des applications réparties. Université Scientifique et Médicale de Grenoble, Grenoble (1982)
Rose, A., Swan, S., Pierce, J., Fernandez, J.-M.: Transaction Level Modeling in SystemC. Open SystemC Initiative (2005)
Salaün, G., Etchevers, X., Palma, N.D., Boyer, F., Coupaye, T.: Verification of a self-configuration protocol for distributed applications in the cloud. In: Proceedings of the 27th Symposium On Applied Computing SAC’12 (Riva del Garda, Italy). ACM, New York (2012, to appear)
Thivolle, D.: Langages modernes pour la vérification des systèmes asynchrones. Thèse de Doctorat, Université Joseph Fourier (Grenoble, France) and Universitatea Politehnica din Bucuresti (Bucharest, Romania), April 2011
Tronel, F., Lang, F., Garavel, H.: Compositional verification using CADP of the ScalAgent deployment protocol for software components. In: Proceedings of the 6th IFIP International Conference on Formal Methods for Open Object-based Distributed Systems FMOODS’2003 (Paris, France). Lecture Notes in Computer Science, vol. 2884, pp. 244–260. Springer, Berlin, Nov 2003. Full version available as INRIA Research Report RR-5012
Wolper, P.: A translation from full branching time temporal logic to one letter propositional dynamic logic with looping. Unpublished manuscript (1982)
Yeh, W.J., Young, M.: Compositional reachability analysis using process algebra. In: Proceedings of the ACM SIGSOFT Symposium on Testing, Analysis, and Verification (SIGSOFT’91, Victoria, British Columbia, Canada), pp. 49–59. ACM Press, New York, Oct 1991