Bringing test to design: testing in the designer's event based environment
Tóm tắt
In this paper, we present a new tester that works in the IC designer's simulation environment instead of traditional ATE test environment. The tester uses IC simulation data from a Verilog or VHDL simulator in the vcd format. The basic tester architecture and its operation are described.
Từ khóa
#Circuit testing #Integrated circuit testing #Design engineering #Costs #Circuit simulation #Hardware design languages #Timing #Signal design #Integrated circuit modeling #Computer architectureTài liệu tham khảo
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