Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET

A detailed investigation of the drift resistance evolution with the gate and drain biases in Lateral DMOS architectures is reported. The extractions are performed using the concept of intrinsic drain voltage, V/sub K/, applied to both simulated and measured data. Some new special test structures (MESDRIFT) have been designed and fabricated in order to investigate the DMOS bias-dependent drift resistance and experimentally confirm 2D numerical simulations. Some of the physical origins, associated with drift resistance dependence on gate and drain bias, are discussed. A simple yet efficient DMOS macro-modeling strategy is reported. It consists of combining a low-voltage BSIM model module with a bias-dependent series resistance described by a quasi-empirical mathematical expression. All LDMOS operation regimes (including quasi-saturation) are captured by the proposed expression and data measured on MESDRIFT is used to calibrate the BSIM and drift parameters. The methodology does not dependent on the drift architecture and can be applied to any similar asymmetric HV MOS devices.