An inner gate as enabler for vertical pitch scaling in macaroni channel gate-all-around 3-D NAND flash memory

Solid-State Electronics - Tập 199 - Trang 108498 - 2023
D. Verreck1, A. Arreghini1, G. Van den bosch1, M. Rosmeulen1
1imec, 3001 Leuven, Belgium

Tài liệu tham khảo

Alsmeier, 2020, Past and Future of 3D Flash, 6.1.1 Yanagihara, 2012, Control gate length, spacing and stacked layer number design for 3D-stackable NAND flash memory, 1 Verreck D, Arreghini A, Schanovsky F, Rzepa G, Stanojevic Z, Mitterbauer F, et al. Understanding the ISPP Slope in Charge Trap Flash Memory and its Impact on 3-D NAND Scaling. In: 2021 IEEE International Electron Devices Meeting. 2021, p. 1–4. Walker, 2009, Sub-50-nm Dual-Gate Thin-Film Transistors for Monolithic 3-D Flash, IEEE Trans Electron Devices, 56, 2703, 10.1109/TED.2009.2030712 Lin, 2011, Read Characteristics of Independent Double-Gate Poly-Si Nanowire SONOS Devices, IEEE Trans Electron Devices, 58, 3771, 10.1109/TED.2011.2164251 Global TCAD Solutions Rel.2022.03, URL http://www.globaltcad.com/.