An experimental 27w 1Mb CMOS high-speed DRAM

In recent years, high-speed DRAMs[ll are in greater demand as microprocessors become faster. In a small microprocessor-based computer system. high-speed DRAMS can keep up with the CPU and avoid wait states during memory accesses. This paper describes an experimental 256 K word X 4 bit CMOS DRAM with a typical RAS access time of 27 ns. In page mode operation, a typical CAS access time of 12 ns with a page cycle time of 24 ns is obtained. This performance was achieved by Strapping wordline with metal, a multiplexed sense amplifier using depletion devices, a fast boosted wordline clock and driver, half - VDD sensing without dummy cells, and segmented 1/0 lines for faster I/O seming. Unique wordline and bitline redundancy is implemented which does not adversely affect access and cycle times. Robust cell-array N-well and substrate bias generators provide low cell leakage current and improve peripheral circuit speed. Bitline margin test done by changing bitline precharge voltage enhances the testability of the memory arrays.