An 8-way VLIW embedded multimedia processor with advanced cache mechanism
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 213-216
Tóm tắt
An 8-way VLIW embedded multimedia processor is developed in 0.11 /spl mu/m 7-layer Cu/Al metal CMOS process technology. The processor achieved the peak performance of 2132 MIPS/2.1 GFLOPS/4.26 GOPS at 533 MHz. This processor equips 4-way integer and 4-way floating/media pipelines. Each media pipeline can execute a 4-parallel SIMD instruction, so 16-operations can be executed at a cycle. It also equips the data and instruction caches, and each of their size is 32 KB. The data cache has a non-aligned data access mechanism and an enhanced store operation mechanism, and a 9% performance improvement was verified. The instruction cache has a reconfigurable associativity mechanism, and achieved more than 12% of power consumption decrease. As a result, this processor achieved more than twice the performance over our previous processor. This processor enables MPEG2 MP@ML 2-stream decoding.
Từ khóa
#VLIW #Pipelines #Laboratories #Energy consumption #CMOS process #Decoding #Microprocessors #Circuits #CMOS technology #Process designTài liệu tham khảo
okano, 2002, An 8-way VLIW Embedded Multimedia Processor Built in a 7-layer Metal 0. 11 m CMOS Technology, ISSCC Digest of Technical Papers
10.1109/40.865863
10.1109/ISSCC.2000.839767
okano, 2000, A 350MHz 5.6GOPS/1.4GFLOPS 4-Way VLIW Embedded Microprocessor, Proc of COOL Chips III, 231