Advanced SOI MOSFETs with buried alumina and ground plane: self-heating and short-channel effects
Tài liệu tham khảo
Frank, 2001, Device scaling limits of Si MOSFETs and their application dependencies, Proc. IEEE, 89, 259, 10.1109/5.915374
Cristoloveanu S. SOI technology: the future will not scale down. In: Huff HR, Fabry L, Kishino S, editors. Semiconductor silicon 2002. The Electrochemical Society Proceedings Series PV 2002-2, Pennington, NJ, 2002. p. 328
Celler, 2003, Frontiers of silicon-on-insulator, J. Appl. Phys., 93, 4955, 10.1063/1.1558223
Cristoloveanu, 2003
Su, 1994, Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET’s, IEEE Electron. Dev. Lett., 15, 183, 10.1109/55.291592
Oh, 2000, Analytic description of short-channel effects in fully-depleted double-gate and cylindrical, surrounding-gate MOSFETs, IEEE Electron. Dev. Lett., 21, 445, 10.1109/55.863106
Yan, 1992, Scaling the Si MOSFET: from bulk to SOI to bulk, IEEE Trans. Electron. Dev., 39, 1704, 10.1109/16.141237
Cristoloveanu, 1995
Su LT, Goodson KE, Antoniadis DA, Flik MI, Chung JE. Measurement and modeling of self-heating effects in SOI n-MOSFETs. In: IEDM Conf, 1992. p. 357
Berger, 1991, Estimation of heat transfer in SOI MOSFETs, IEEE Trans. Electron. Dev., 38, 871, 10.1109/16.75217
Yachou D, Gautier J, Raynaud C. Self-heating effects on static and dynamic SOI operation. In: Proc ESSDERC Conf, Frontieres, Gif-sur-Yvette, France, 1993. p. 695
Colinge, 1997
Bernstein, 2000
Oshima K, Cristoloveanu S, Guillaumot B, Carval GL, Deleonibus S, Iwai H, et al. Novel SOI-like structures for improved thermal dissipation. In: Proc IEEE Int SOI Conf, 2002. p. 95
Oshima K, Cristoloveanu S, Guillaumot B, Carval GL, Iwai H, Mazure C, et al. Replacing the BOX with buried alumina: improved thermal dissipation in SOI MOSFETs. In: Cristoloveanu S, Celler GK, Fossum JG, Gamiz F, Izumi K, Kim Y-W, editors. Silicon-on-insulator technology and devices XI. The Electrochemical Society Proceedings Series PV 2003-05, Pennington, NJ, 2003. p. 45
Luryi S. Private communication, 2003
Nakayama H, Nakamura M, Komatsu H, Hu C. SOI MOSFET thermal conductance and its geometry dependence. In: Proc IEEE Int SOI Conf, 2000. p. 128
Shackelford, 2000
Ernst T, Cristoloveanu S. Ground-plane concept for reduction of short-channel effects in fully-depleted SOI devices. In: Hemment PLF, Cristoloveanu S, Houston TW, Izumi K, Hovel H, editors. Silicon-on-insulator technology and devices IX. The Electrochemical Society Proceedings Series PV 99-3, Pennington, NJ, 1999. p. 329
Yeh, 1995, Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology, IEEE Trans. Electron. Dev., 42, 1605, 10.1109/16.405274
Ernst, 2002, Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture, Solid-State Electron., 46, 373, 10.1016/S0038-1101(01)00111-3
Xiong W, Ramkumar K, Jang SJ, Park J-T, Colinge J-P. Self-aligned ground-plane FDSOI MOSFET. In: Proc IEEE Int SOI Conf, 2002. p. 23
Xiong, 1999, Self-aligned implanted ground-plane fully depleted SOI MOSFET, Electron. Lett., 35, 2059, 10.1049/el:19991390
Bain MF, McCusker ND, McCann P, Nevin WA, Gamble HS. Back-end analysis of SOI substrates incorporating metallic layers using a novel non-destructive picosecond ultrasonic technique. In: Cristoloveanu S, Celler GK, Fossum JG, Gamiz F, Izumi K, Kim Y-W, editors. Silicon-on-insulator technology and devices XI. The Electrochemical Society Proceedings Series PV 2003-05, Pennington, NJ, 2003. p. 63
