Accelerated techniques in stem fault simulation
Tóm tắt
In order to cope with the most expensive stem fault simulation in fault simulation field, several accelerated techniques are presented in this paper. These techniques include static analysis on circuit structure in preprocessing stage and dynamic calculations in fault simulation stage. With these techniques, the area for stem fault simulation and number of the stems requiring explicit fault simulation are greatly reduced, so that the entire fault simulation time is substantially decreased. Experimental results given in this paper show that the fault simulation algorithm using these techniques is of very high efficiency for both small and large numbers of test patterns. Especially with the increase of circuit gates, its effectiveness improves obviously.
Tài liệu tham khảo
Abramovici M, Breuer M A, Friedman A D. Digital Systems Testing and Testable Design. New York, Computer Science Press, 1990.
Hong S J. Fault simulation strategy for combinational logic networks. InProc. 8th Int’l Symp. Fault-Tolerant Computing, 1978, pp.96–99.
Abramovici M, Menon P R, Miller D T. Critical path tracing—An alternative to fault simulation. InProc. 20th Design Automation Conference, 1983, pp.214–219.
Wei Daozhenget al. Automatic diagnosis for faults in digital logic circuits.Developments in Electronic Computers, 1976, 13: 1–8.
Waicukauski J A, Eichelberger E B, Forlenza D O, Lindbloom E, McCarthy T. Fault simulation for structured VLSI.VLSI Syst. Design, 1985, 12: 20–32.
Antreich K, Schulz M. Accelerated fault simulation and fault grading in combinational circuits.IEEE Trans. on Computer-Aided Design, 1987, CAD-6(9): 704–712.
Maamari F, Rajski J. A fault simulation method based on stem regions. InICCAD-88, 1988, pp.170–173.
Wei Daozheng. Parallel critical path tracing—A fault simulation algorithm for combinational circuits.Chinese Journal of Computers, 1988, 11(7): 408–515. (in Chinese)
Wei Daozheng. An improvement of the critical path tracing method.Journal of Computer-Aided Design & Computer Graphics, 1989, 1(1): 70–74. (in Chinese).
Underwood B, Ferguson J. The parallel-test-detect fault simulation algorithm. InProc. Int’l Test Conf., 1989, pp.712–717.
Smith S P. An enhanced high performance combinational fault simulator using two-way parallelism. InInt’l Conf. on Computer Design, 1989, pp.294–297.
Lee H K, Ha D S. An efficient, forward fault simulation algorithm based on the parallel pattern single fault propagation. InProc. Int’l Test Conf., 1991, pp.946–955.
Song O, Menon P R. Acceleration of trace-based fault simulation of combinational circuits.IEEE Trans. on CAD, 1993, 12(9): 1413–1419.
Brglez F, Fujiwara H. A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. InProc. Int’l Symp. on Circuits and Systems, 1985, pp.663–698.