Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al2O3 gate dielectric

Applied Physics Letters - Tập 108 Số 3 - 2016
Yu-Hong Chang1, Ming-Jiue Yu1, Ruei-Ping Lin1, Chih-Pin Hsu1, Tuo‐Hung Hou1
1National Chiao Tung University Department of Electronics Engineering and Institute of Electronics, , Hsinchu, Taiwan

Tóm tắt

Low-temperature atomic layer deposition (ALD) was employed to deposit Al2O3 as a gate dielectric in amorphous In–Ga–Zn–O thin-film transistors fabricated at temperatures below 120 °C. The devices exhibited a negligible threshold voltage shift (ΔVT) during negative bias stress, but a more pronounced ΔVT under positive bias stress with a characteristic turnaround behavior from a positive ΔVT to a negative ΔVT. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive ΔVT, which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al2O3 is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In–Ga–Zn–O channel and induce the negative ΔVT through electron doping with power-law time dependence. A rapid partial recovery of the negative ΔVT after stress is also observed during relaxation.

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Applied Physics Letters

Tập 108 Số 3

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