ALTICS: an advanced timing analysis system for VLSI

Timing verification is one of the most difficult tasks In logic LSI designing. For example, in designing ASICs using automatic layout. despite the dispersion of wiring length has to be considered in clocking skew or setup/hold verification before the Layout. logic simulator cannot deal with such kinds of problems. and has a shortcoming that it can verify only those which can be activated by a given test pattern. The path analysis [I1 C21 Is another approach, however, it has a possibility to detect the paths that cannot be activated and is only available for simply synchronized circuits