A speed enhancement DRAM array architecture with embedded ECC

Symposium 1989 on VLSI Circuits - 1989
Arimoto1, Matsuda1, Furutani1, Tsukude1, Oisiii, Mashiko1, Fujishima1
1LSI R & D Laboratory, Mitsubishi Electric Corporation Limited, Itami, Japan

Tóm tắt

A scaling down principle brings a high speed switching and a low power dissipation with the reliability maintained [I-21. In addition to the dimension scaling down. an epoch-making array architecture with the countermeasure of smaller signal charge is required in a high speed 16MbDRAH.

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#Computer architecture #Arrays #Microprocessors #Error correction codes #Random access memory #Logic gates #Distributed databases

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Symposium 1989 on VLSI Circuits

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