A novel self-repairable parallel multiplier architecture, design and test

Rong Lin1, M. Margala2, N. Kazakova3
1Computer Science, State University of New York, Geneseo, NY, USA
2Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA
3Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada

Tóm tắt

A novel, self-repairable, parallel multiplier architecture with high speed low power CMOS parallel counter circuits and design-for-test (DFT) implementations is presented. The illustrated 16/spl times/16-b multiplier architecture can be easily reconfigured into 17 different architectures for fault recovering. Also described is a novel verification scheme that performs exhaustive data validation. Compared to previous parallel multiplier architectures, the proposed multiplier architecture has reduced transistor count, enhances yield using built-in self-repair mechanism and provides high performance at low-voltages. The proposed exhaustive DFT technique greatly reduces the test vector length required to verify the data validity, from 17*2/sup 32/ vectors needed in a conventional architecture to only 1.3*2/sup 13/ vectors needed in this architecture. Furthermore, the concepts presented are scalable to larger multiplier architectures.

Từ khóa

#Automatic testing #Circuit testing #Circuit faults #Adders #Computer architecture #Concurrent computing #Power engineering computing #Design engineering #Power engineering and energy #Power system reliability

Tài liệu tham khảo

lin, 1999, Parallel VLSI Shift Switch Logic Devices, A family of high performance multipliers and matrix multipliers lin, 2001, Reconfigurable Parallel Inner Product Processor Architectures, IEEE Transactions on very large scale integration Systems, 9, 261, 10.1109/92.924037 10.1109/92.988727 10.1109/4.52161 weste, 1993, Principles of CMOS VLSI Design A System Perspective margala, 2001, Design verification and DFT for an Embeddded reconfigurable low-power multiplier in system-on-chip applications, Proceedings of the 14th Annual IEEE International ASIC/SoC Conference, 230, 10.1109/ASIC.2001.954703 10.1109/ISCAS.2001.922320 10.1109/4.792613 10.1109/JSSC.1987.1052811 10.1155/2001/97598 10.1109/4.938377 10.1109/4.641687