A low power, wide operating frequency and high noise immunity half-digital phased-locked loop
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 263-266
Tóm tắt
In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.
Từ khóa
#Frequency #Phase noise #Voltage-controlled oscillators #Phase locked loops #Power dissipation #Circuit noise #Voltage control #Jitter #Phase detection #FiltersTài liệu tham khảo
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