A latch-up like new failure mechanism for high density cmos dynamic RAM's - hysteresis in operating Vcc range

AS the RAM has reached higher Integration, transistors have been miniaturized as well as the number of transistors on a chip has increased. Therefore, the substrate current generated by the RAM circuit due to impact ionization has increased drastically. In addition, since substrate impurity concentration has increased with the device scaling, the back-gate bias effect of a transistor has become stronger. The same discussion can be adopted for the well concentration of the CMOS DRAM, which has been a standard since the 1M era.