A 68ns 4Mbit CMOS EPROM with high noise immunity design

Symposium 1989 on VLSI Circuits - 1989
Imamiya1, Miyamoto, Ohtstika, Atsurni, Sako2, Muroya2, Mori2, Yoshikawa, Tanaka
1TOSHIBA Corp.
2Scrmconductor Device Engineering Laboratory, Toshiba Corporation, Kawasaki, Japan

Tóm tắt

High speed non-volatile memories with large bit density have been required for high performance micro-processor systems. Sub 100ns-access time 4Mbit EPROMs[1], [2] have been, developed to meet the marlre1 needs.

Từ khóa

#EPROM #Capacitance #Dams #Logic gates #Threshold voltage #Sensors #Delays

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Symposium 1989 on VLSI Circuits

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