A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique
Proceedings. IEEE Asia-Pacific Conference on ASIC, - Trang 181-184
Tóm tắt
A CMOS comparator operating over a 1 V to 5 V supply range is presented. No special low-voltage technology is used for fabrication. An experimental chip was fabricated using a 0.5 /spl mu/m 5 V CMOS double-poly double-metal technology. The chip area of the comparator was 230/spl times/160 /spl mu/m/sup 2/. Measured results at 1 V supply voltage show a comparator response time of less than 4 /spl mu/s for 10 mV precision. Static power consumptions at 1 V supply voltage including input/output pads for comparator is 1 /spl mu/W.
Từ khóa
#Preamplifiers #Sampling methods #Parasitic capacitance #Switches #CMOS technology #Low voltage #Energy consumption #Capacitors #Semiconductor device measurement #Time measurementTài liệu tham khảo
10.1109/4.173122
10.1109/4.148325
10.1049/el:20000369
bruccoleri, 1996, offset reduction technique for use with high speed cmos comparators, Electronics Letters, 32, 1193, 10.1049/el:19960775
10.1109/19.199421
10.1109/81.662703
10.1109/4.551918
10.1109/4.127344
10.1109/4.668991
10.1109/4.90034