Measurement challenges for on-wafer RF-SOC test

With the wireless industry pushing towards higher levels of integration, with more system-in-a-package (SIP) and multi-chip module (MCM) technology, known-good-die testing of RF-SOC devices has emerged as the next test challenge. These devices have higher packaging costs compared to the traditional single die integrated circuits (ICs), and potential lower yields, since multiple dice are used. As a result, the cost to perform comprehensive on-wafer testing is outweighed by the cost to scrap the devices during the final package test. In addition, some IC manufacturers are selling bare die to be used in the SIP or MCM of another manufacturer. On-wafer test is then required to ensure that good product is shipped. This paper will use a Bluetooth radio modem chip as an example to discuss the measurement challenges and considerations for known-good die testing of a RF-SOC device. With this example, the difficulty of testing RF functionality on-wafer will be compounded by the need to source and measure RF and digital signals simultaneously, creating signal integrity issues. This paper will explore the challenges of laying out the printed circuit board for the device under test (DUT), including setup of the wafer probe card and assembly. Factors taken into account when selecting a probe station, RF wafer probe card, and ATE test system will then be discussed. This paper will conclude with a discussion of on-wafer calibration, including challenges and solutions. Real results from the Bluetooth radio modem chip example will be used to further the discussion.