Impact of on- and off-chip protection on the transient-induced latch-up sensitivity of CMOS IC

Microelectronics Reliability - Tập 57 - Trang 53-58 - 2016
Mirko Scholz1, Shih-Hung Chen1, Geert Hellings1, Dimitri Linten1
1IMEC, Kapeldreef 75, B-3001 Leuven, Belgium

Tài liệu tham khảo

“JESD-78D - IC Latch-Up Test”, JEDEC 2011. ESDA, 2012 Brodbeck, 2011, Triggering of transient latch-up by system-level ESD, IEEE Trans. Device Mater. Reliab., 11, 509, 10.1109/TDMR.2011.2165072 Scholz, 2012, Mixed-mode simulations for power-on ESD analysis, 379 DECIMM – http://www.angstromda.com. Ker, 2006, Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations, IEEE Trans. Device Mater. Reliab., 6, 461, 10.1109/TDMR.2006.882203 Scholz, 2009, ESD on-wafer characterization: Is TLP still the right measurement tool?, IEEE Trans. Instrum. Meas., 58, 3418, 10.1109/TIM.2009.2017657 Willemen, 2003, Characterization and modeling of transient device behavior under CDM ESD stress Liang, 1990, Diode forward and reverse recovery model for power electronic spice simulations, IEEE Trans. Power Electron., 5, 346, 10.1109/63.56526 Johnsson, 2011, Study of system ESD codesign of a realistic mobile board Scholz, 2012, System-level ESD protection design using on-wafer characterization and transient simulations Suzuki, 2006, A study of relation between a power supply ESD and parasitic capacitance, J. Electrost., 64, 760, 10.1016/j.elstat.2006.05.007