Thermal-Aware Post Layout Voltage-Island Generation for 3D ICs

Hua H, Mineo C, Schoenfliess K, Sule A, Melamed S, Jenkal R, Davis W R. Exploring compromises among timing, power and temperature in three-dimensional integrated circuits. In Proc. the 43th Design Automation Conference, June 2006, pp.997-1002.

Hu J, Shin Y, Dhanwada N, Marculescu R. Architecting voltage-islands in core based system-on-a-chip designs. In Proc. Int. Symp. Low Power Electronics and Design, August 2004, pp.180-185.

Hung W, Link G, Xie Y, Vijaykrishnan N, Dhanwadaf N, Conner J. Temperature-aware voltage islands architecting in system-on-chip design. In Proc. IEEE International Conference on Computer Design, October 2005, pp.689-696.

Mak W K, Chen J W. Voltage island generation under performance requirement for SoC designs. In Proc. Asia and South Pacific Design Automation Conference, January 2007, pp.798-803.

Lee W P, Liu H Y, Chang Y W. Voltage island aware floor-planning for power and timing optimization. In Proc. International Conference on Computer-Aided Design, November 2006, pp.389-394.

Lee W P, Liu H Y, Chang Y W. An ILP algorithm for post-floorplanning votage-island generation considering power-network planning. In Proc. International Conference on Computer-Aided Design, November 2007, pp.650-655.

Ma Y C, Qiu X, He X Q, Hong X L. Incremental power optimization for multiple supply voltage design. In Proc. International Symposium on Quality of Electronic Design, March 2009, pp.280-286.

Yu S A, Huang P Y, Lee Y M. A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects. In Proc. Asia and South Pacific Design Automation Conference, January 2009, pp.55-60.

Cong J, Wei J, Zhang Y. A thermal-driven floorplanning algorithm for 3D ICs. In Proc. International Conference on Computer-Aided Design, November 2004, pp.306-313.

Hung W L, Link G M, Xie Y, Vijaykrishnan N, Irwin M J. Interconnect and thermal-aware floorplanning for 3D micro-processors. In Proc. the 7th International Symposium on Quality Electronic Design, March 2006, pp.98-104.

Yu H, Ho J, He L. Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity. ACM Transactions on Design Automation of Electronic Systems (TO-DAES), 2009, 14(3): Article No. 41.

Yu H, Shi Y, He L, Karnik T. Thermal via allocation for 3D ICs considering temporally and spatially variant thermal power. IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2008, 16(12): 1609–1619.

Wilkerson P, Raman A, Turowski M. Fast, automated thermal simulation of three-dimensional integrated circuits. In Proc. the 9th Intersociety Conference on Thermal and Thermo-mechanical Phenomena in Electronic Systems, June 2004, pp.706-713.

Cong J, Zhang Y. Thermal via planning for 3-D ICs. In Proc. International Conference on Computer-Aided Design, November 2005, pp.745-752.

Cong J, Zhang Y. Thermal-driven multilevel routing for 3-D ICs. In Proc. Asia and South Pacific Design Automation Conference, January 2005, pp.121-126.

Cheng Y, Tsai C, Teng C, Kang S. Electrothermal Analysis of VLSI Systems. Springer, 2000.

Ma Y C, Li X, Wang Y, Hong X L. Thermal-aware incremental floorplanning for 3D ICs based on MILP formulation. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2009, E92-A(12): 2979–2989.