Design Automation for Embedded Systems
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Influence of different abstractions on the performance analysis of distributed hard real-time systems
Design Automation for Embedded Systems - Tập 13 - Trang 27-49 - 2008
System level performance analysis plays a fundamental role in the design process
of hard real-time embedded systems. Several different approaches have been
presented so far to address the problem of accurate performance analysis of
distributed embedded systems in early design stages. The existing formal
analysis methods are based on essentially different concepts of abstraction.
However, the influ...
SBESC 2014 guest editors’ introduction
Design Automation for Embedded Systems - Tập 20 - Trang 93-94 - 2016
Reducing the complexity of instruction-level power models for VLIW processors
Design Automation for Embedded Systems - Tập 10 - Trang 49-67 - 2006
Aim of this paper is to propose a high-level power exploration framework based
on an instruction-level energy model for VLIW (Very Long Instruction Word)
architectures. More specifically, the present paper deals with the reduction of
the complexity of the energy model of K-issue VLIW processors from exponential
with respect to the number of operations within the Instruction Set O(⫨ISA⫨ K )
to quad...
Energy efficient scheduling algorithm for the multicore heterogeneous embedded architectures
Design Automation for Embedded Systems - Tập 22 - Trang 1-12 - 2018
In the world of embedded architectures, energy consumption and the reliable
performance are the two important parameters where the limelight of the research
is required. When embedded architectures are used as the Internet of Things,
these two parameters plays the very important role in the better performance.
Several algorithms have been designed for the energy consumption in the embedded
archite...
Retraction Note to: Online measurement of water quality and reporting system using prominent rule controller based on aqua care-IOT
Design Automation for Embedded Systems - Tập 26 - Trang 131-131 - 2022
A hardware/software partitioning method based on graph convolution network
Design Automation for Embedded Systems - Tập 25 - Trang 325-351 - 2021
Hardware/software (HW/SW) partitioning is the crucial step in HW/SW co-design,
which can significantly reduce the time-to-market and improves the performance
of an embedded system. Due to that the majority of previous works have large
exploration time and generate often low-quality solutions for large scale
systems, we propose a fast HW/SW partitioning approach based on graph
convolution network (...
DesertFD: a finite-domain constraint based tool for design space exploration
Design Automation for Embedded Systems - - 2010
SRCP: sharing and reuse-aware replacement policy for the partitioned cache in multicore systems
Design Automation for Embedded Systems - Tập 25 - Trang 193-211 - 2021
Although multi-core processors enhance the performance yet the challenge of
estimating Worst-Case Execution Time (WCET) of a task remains in such systems
due to interference in shared resources like Last Level Caches (LLC). Cache
partitioning has been used to reduce the interference problem by isolating the
shared cache among each thread to ease the WCET estimation. However, it prevents
informatio...
Self-aware Memory: an adaptive memory management system for upcoming manycore architectures and its decentralized self-optimization process
Design Automation for Embedded Systems - Tập 17 - Trang 739-769 - 2014
The number of cores per processor has been increased on and on in recent years.
Carrying on with that, manycore processor systems will be the future system
structure, and even within range for usage in desktop or mobile systems. But
today’s manycore processors are primarily designed for high performance
applications. Access to the external memory from the individual cores is
avoided. As yet the sy...
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