WITHDRAWN: “Improved e-IpDFT for Synchrophasor Estimation implemented in an FPGA-based Controller”

Arpan Malkhandi1, Tirthadip Ghose1
1Department of Electrical and Electronics Engineering, Birla Institute of Technology, Mesra, Ranchi, India

Tài liệu tham khảo

IEEE Std. C37.118.2011-1, IEEE Standard for Synchrophasor Measurements for Power Systems, revision of the IEEE std.C37.118.1-2011-2. Phadke, 2008 Paolo, 2014, Enhanced Interpolated-DFT for Synchrophasor Estimation in FPGAs: Theory, Implementation and Validation of a PMU Prototype”, IEEE Transactions On Instrumentation And Measurement, 63, 2824, 10.1109/TIM.2014.2321463 Magnus, 2010, Sample Value Adjustment Improves PhasorEstimation At Off- Nominal Frequencies, IEEE Transactions On Power Delivery, 25, 2255, 10.1109/TPWRD.2010.2052114