V-CastNet3D: A novel clustering-based mapping in 3-D Network on chip
Tài liệu tham khảo
Bayar, 2015, PFMAP: Exploitation of particle filters for network-on-chip mapping, IEEE Trans. Very Large Scale Integr. Syst., 23, 2116, 10.1109/TVLSI.2014.2360791
Pang, 2015, Task mapping and mesh topology exploration for an fpga-based network on chip, Microprocess. Microsyst., 39, 189, 10.1016/j.micpro.2015.03.006
A. Pullini, et al., NoC design and implementation in 65 nm technology, in: Proc. - NOCS 2007 First Int. Symp. Networks-on-Chip, 2007, pp. 273–282.
Qian, 2016, Performance evaluation of NoC-based multicore systems: From traffic analysis to NoC latency modeling, ACM Trans. Des. Autom. Electron. Syst., 21, 52:1
Sahu, 2013, A survey on application mapping strategies for network-on-chip design, J. Syst. Archit., 59, 60, 10.1016/j.sysarc.2012.10.004
Sahu, 2014, Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization, IEEE Trans. Very Large Scale Integr. Syst., 22, 300, 10.1109/TVLSI.2013.2240708
Tosun, 2011, New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs, J. Syst. Archit., 57, 69, 10.1016/j.sysarc.2010.10.001
V. Jha, S. Deol, M. Jha, G.K. Sharma, Energy and latency aware application mapping algorithm & optimization for homogeneous 3D network on chip keywords network on chip, mapping, 3D architecture, system on chip, optimization.
W. Jiawen, L.I. Li, W. Zhongfeng, Z. Rong, Z. Yuang, Energy-efficient mapping for 3D NoC using, 23(2) (2014).
P.K. Hamedani, S. Hessabi, H. Sarbazi-Azad, N.E. Jerger, Exploration of temperature constraints for thermal aware mapping of 3D networks on chip, in: Proc. - 20th Euromicro Int. Conf. Parallel, Distrib. Network-Based Process. PDP 2012, 2012, pp. 499–506.
Huang, 2016, Low-power mapping algorithm for three-dimensional network-on-chip based on diversity-controlled quantum-behaved particle swarm optimization, J. Algorithm. Comput. Technol., 10, 176, 10.1177/1748301816649070
Ge, 2013, Power-and thermal-aware mapping for 3d network-on-chip, Inf. Technol. J., 12, 7297, 10.3923/itj.2013.7297.7304
Mosayyebzadeh, 2016, Thermal and power aware task mapping on 3D Network on Chip, Comput. Electr. Eng., 51, 157, 10.1016/j.compeleceng.2015.12.001
Murali, 2004, Bandwidth-constrained mapping of cores onto NoC architectures, Proc. - Des. Autom. Test Eur. Conf. Exhib., 2, 896, 10.1109/DATE.2004.1269002
I. Anagnostopoulos, A. Bartzas, I. Vourkas, D. Soudris, Node resource management for dsp applications on 3D network-on-chip architecture, in: DSP 2009 16th Int. Conf. Digit. Signal Process. Proc. 2009.
C.C. Systems, S. Guo, Survey on mapping algorithm of three-dimensional network on chip, 2016.
Kapadia, 2016, A system-level cosynthesis framework for power delivery and on-chip data networks in application-specific 3-D ICs, IEEE Trans. Very Large Scale Integr. Syst., 24, 3, 10.1109/TVLSI.2015.2399279
Taassori, 2016, Fuzzy-based mapping algorithms to design networks-on-chip, J. Intell. Fuzzy Syst., 31, 27, 10.3233/IFS-162105
Saha, 2010, A symmetry based multiobjective clustering technique for automatic evolution of clusters, Pattern Recognit., 43, 738, 10.1016/j.patcog.2009.07.004
Bandyopadhyay, 2007, GAPS: A clustering method using a new point symmetry-based distance measure, Pattern Recognit., 40, 3430, 10.1016/j.patcog.2007.03.026
Fang, 2015, KL_GA: an application mapping algorithm for mesh-of-tree (MoT) architecture in network-on-chip design, J. Supercomput., 71, 4056, 10.1007/s11227-015-1504-y