Two advanced energy-back SAR ADC architectures with 99.21 and 99.37 % reduction in switching energy
Tóm tắt
Từ khóa
Tài liệu tham khảo
Zhu, Z., Qiu, Z., Liu, M., & Ding, R. (2015). A 6-to-10-bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 n++ CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 62, 689–696.
Zhu, Z., & Liang, Y. (2015). A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-um CMOS for medical implant devices. IEEE Transactions on Circuits and Systems I: Regular Papers, 62, 2167–2176.
Bocharov, Y. I., Butuzov, V., & Simakov, A. (2015). A multichannel analog-to-digital converter of signals of silicon photomultiplier arrays. Instruments and Experimental Techniques, 58(5), 623–630.
Liu, C.-C., Chang, S.-J., Huang, G.-Y., & Lin, Y.-Z. (2010). A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. IEEE Journal of Solid-State Circuits, 45, 731–740.
Sanyal, A., & Sun, N. (2013). SAR ADC architecture with 98 % reduction in switching energy over conventional scheme. Electronics Letters, 49, 248–250.
Xie, L., Wen, G., Liu, J., & Wang, Y. (2014). Energy-efficient hybrid capacitor switching scheme for SAR ADC. Electronics Letters, 50, 22–23.
Yuan, C., & Lam, Y. (2012). Low-energy and area-efficient tri-level switching scheme for SAR ADC. Electronics Letters, 48, 482–483.
Srinivasan, S., & Balsara, P. (2014). Energy-efficient sub-DAC merging scheme for variable resolution SAR ADC. Electronics Letters, 50, 1421–1423.
Wei, L., Duona, L., Fengcheng, M., Jiaqi, Y., Libin, Y., Lin, H., et al. (2014). A 0.6 V 10 bit 1 MS/s monotonic switching SAR ADC with common mode stabilizer in 0.13 μm CMOS. Journal of Semiconductors, 35(5), 055006.
Zhu, Z., Xiao, Y., & Song, X. (2013). VCM-based monotonic capacitor switching scheme for SAR ADC. Electronics Letters, 49, 327–329.
Song, H., & Lee, M. (2014). Asymmetric monotonic switching scheme for energy-efficient SAR ADCs. IEICE Electronics Express, 11(12), 20140345–20140345.
Anand, T., Chaturvedi, V., & Amrutur, B. (2010). Energy efficient asymmetric binary search switching technique for SAR ADC. Electronics letters, 46(22), 1487–1488.
Wang, H., Zhu, Z., & Ding, R. (2015). Energy-efficient and area-efficient tri-level floating capacitor switching scheme for SAR ADC. Analog Integrated Circuits and Signal Processing, 85(2), 373–377.
Wang, H., & Zhu, Z. (2015). Energy-efficient and area-efficient switching scheme based on multi-reference for SAR ADC. IEICE Electronics Express, 12(4), 20141182–20141182.
Tong, X., Zhang, W., & Li, F. (2014). Low-energy and area-efficient switching scheme for SAR A/D converter. Analog Integrated Circuits and Signal Processing, 80(1), 153–157.
Sanyal, A., & Sun, N. (2014). An energy-efficient low frequency-dependence switching technique for SAR ADCs. IEEE Transactions on Circuits and Systems II: Express Briefs, 61, 294–298.
Tong, X., & Zhang, Y. (2015). 98.8 % Switching energy reduction in SAR ADC for bioelectronics application. Electronics Letters, 51(14), 1052–1054.
Tong, X., & Ghovanloo, M. (2015). Energy-efficient switching scheme in SAR ADC for biomedical electronics. Electronics Letters, 51(9), 676–678.
Liang, Y., Zhu, Z., & Ding, R. (2015). SAR ADC architecture with 98.8 % reduction in switching energy over conventional scheme. Analog Integrated Circuits and Signal Processing, 84(1), 89–96.
Huang, G.-Y., Chang, S.-J., Liu, C.-C., & Lin, Y.-Z. (2013). 10-bit 30-MS/s SAR ADC using a switchback switching method. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21, 584–588.
Ding, Z., Bai, W., & Zhu, Z. (2016). Trade-off between energy and linearity switching scheme for SAR ADC. Analog Integrated Circuits and Signal Processing, 86(1), 121–125.
Lin, M.-H., He, Y.-T., Hsiao, V.-H., Chang, R.-G., & Lee, S.-Y. (2013). Common-centroid capacitor layout generation considering device matching and parasitic minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32, 991–1002.
Bocharov, Y., & Butuzov, V. (2015). A low-power ASIC containing 10 analog-to-digital converters and buffer memory. In 2015 International Siberian conference on control and communications (SIBCON) (pp. 1–3).
Anderson, T. (1972). Optimum control logic for successive approximation analog-to-digital converters. Deep Space Network Progress Report, 13, 168–176.