Theoretical properties of LFSRs for built-in self test

Williams, 1982, Design for testability – a survey, IEEE Trans. Comput., C-31, 2, 10.1109/TC.1982.1675879 V.D. Agrawal et al., Built-in self test for digital integrated circuits, AT&T Tech. J. 73 (2) (March–April 1994). T. Savaria et al., Automatic test point insertion for pseudo-random testing, Proc. Int. Symp. on Circuits and Systems, 1991. B.H. Seiss, P.M. Trouborst, M.H. Schulz, Test point insertion for scan-based BIST, Proc. European Test Conf., 1991. S.K. Gupta, D.K. Pradhan, Utilization of on-line (concurrent) checkers during built-in self test and vice-versa, IEEE Trans. Computers 45 (1) (Jan. 1996). E.J. McCluskey, Verification testing – a pseudoexhaustive test technique, IEEE Trans. Computers C-33 (6) (June 1984). L.T. Wang, E.J. McCluskey, Circuits for pseudo-exhaustive test pattern generation, IEEE Trans. Comput. Aided Des. 7 (10) (Oct. 1988). R. David, G. Blanchet, About random fault detection of combinational networks, IEEE Trans. Comput. (June 1976) 650–664. E.B. Eichebelger, E. Lindbloom, Random Pattern coverage Enhancement and Diagnosis for LSSD Logic Self Test, IBM J. Res. Dev. 27 (May 1983) 265–272. H.J. Wunderlich, Self-test using unequiprobable random patterns, Proc. Fault Tolerance in Computer Systems, 1987, pp. 258–263. H.J. Wunderlich, On computing optimized input probabilities for random tests, Proc. Des Automation Conf., 1987, pp. 392–398. J. Hartmann, G. Kemnitz, How to do weighted random for BIST, Proc. Int. Conf. on Comput. Aided Design, 1993, pp. 568–571. Bardell, 1987 C. Dufaza, G. Cambon, LFSR based deterministic and pseudo-random test pattern generator structures, Proc. European Test Conf., 1991, pp. 27–34. S.K. Mukund, E.J. McCluskey, T.R.N. Rao, An apparatus for pseudo-deterministic testing, Proc. VLSI Test Symp., 1995, pp. 125–131. S.B. Akers, W. Jansz, Test set embedding in a built-in self-test environment, Proc. Int. Test Conf., 1989, pp. 257–263. N.A. Touba, E.J. McCluskey, Transformed pseudo-random patterns for BIST, Proc. VLSI Test Symp., 1995. M. Chatterjee, D.K. Pradhan, A novel pattern generator for near-perfect fault-coverage, Proc. VLSI Test Symp., 1995. H.J. Wunderlich, G. Kiefer, Scan-based BIST with complete fault coverage and low hardware overhead, IEEE European Test Workshop, June 1996. E.J. Cluskey et al., Probability models for pseudorandom test sequences, IEEE Trans. Computer-Aided Design, Jan. 1988. J.A. Waicukauski et al., Fault simulation for structured VLSI, VLSI Systems Design, Dec. 1985. E.B. Eichebelger, E. Lindbloom, Random pattern coverage enhancement and diagnosis for LSSD logic self test, IBM J. Res. Dev. 27 (May 1983) 265–272. B. Konemann, LFSR-coded test patterns for scan designs, Proc. European Test Conf., 1991. S. Hellebrand, S. Tarnick, J. Rajski, Generation of vectors patterns through reseeding of multiple polynomial linear feedback shift registers, Proc. Int. Test Conf., 1992, pp. 120–129. M. Lempel, S.K. Gupta, M.A. Breuer, Test embedding with discrete logarithms, Proc. VLSI Test Symp., May 1994. C. Dufaza, H. Viallon, C. Chevalier, BIST hardware generator for mixed test scheme, Proc. European Des. and Test Conf. 1995. D. Kagaris, S. Tragoudas, Generating deterministic unordered test patterns with counters, Proc. VLSI Test Symp., May 1996, pp. 374–379. V.K. Agarwal, E. Cerny, Store and generate built-in testing approach, Proc. Fault Tol. Comp. Systems, June 1981, 35–40. W. Daehn, J. Mucha, Hardware test pattern generation for built-in testing, Proc. of Int. Test Conf., 1981, pp. 110–113. M.E. Aboulhamid, E. Cerny, A class of test generators for built-in-testing, IEEE Trans. Comput., 1983, pp. 957–959. R. Dandapani, J. Patel, J. Abraham, Design of test pattern generators for built-in test, Proc. Int. Test Conf., Oct. 1984, pp. 315–319. W. Starke, Built-in test for CMOS circuits, Proc. Int. Test Conf., 1984, pp. 309–314. L.F.C. Lew Yan Voon, C. Dufaza, C. Landrault, BIST linear generator based on complemented outputs, IEEE VLSI Test Symp., April 1992. C. Dufaza, C. Chevalier, L.F.C. Lew Yan Voon, LFSROM an algorithm for automatic design synthesis of hardware test pattern generator, Proc. VLSI Test Symp., April 1993, pp. 208–214. C.J. Lin, S.M. Reddy, On delay fault testing in logic circuits, IEEE Trans. Comput. Aided Design, 6 (5) (Sept. 1987) 694–703. A.K. Pramanick, S.M. Reddy, On the detection of delay faults, Proc. Int. Test Conf., Oct. 1988, pp. 845–856. G.L. Smith, Model for delay faults based upon paths, Proc. Int. Test Conf., Nov. 1985, pp. 342–349. I. Voyiatzis et al., Accumulator-based BIST approach for stuck-open and delay faults testing, Proc. European Des. Test Conf., 1995, pp. 431–435. G.L. Craig, C.R. Kime, Pseudo-exhaustive adjacency testing: a BIST approach for stuck-open faults, Proc. Int. Test Conf., Oct. 1985, pp. 126–137. A. Vuksic, K. Fuchs, A new BIST approach for delay fault testing, Proc. European Des. Test Conf., 1984, pp. 284–288. B. Wurth, K. Fuchs, A BIST approach to delay fault testing with reduced test length, Proc. European Des. Test Conf., 1995, pp. 418–483. K. Furuya, E.J. McCluskey, Two-pattern test capabilities of autonomous TPG Circuits, Proc. Int. Test Conf., 1991, pp. 704–711. K. Furuya, S. Yamazaki, M. Sato, Evaluations of various TPG circuits for use in two-pattern testing, Proc. VLSI Test Symp., May 1994, 242–247. C. Chen, S.K. Gupta, BIST test pattern generators for stuck-open and delay testing, Proc. European Des. Test Conf., 1994, pp. 289–296. S. Zhang, R. Byrne, D.M. Miller, BIST generators for sequential faults, Proc. ICCD, 1992, pp. 260–263. D.K. Pradhan, M. Chatterjee, GLFSR – a new test pattern generator for built-in self test, Proc. Int. Test Conf., 1994, pp. 481–490. S. Pilarski, A. Pierzynska, BIST and delay fault detection, Proc. Int. Test Conf., Oct. 1993, pp. 236–242. C. Chen, S.K. Gupta, BIST test pattern generators for two-pattern testing – theory and design algorithms, IEEE Trans. Comput. 45 (3) (March 1996) 257–269. W. Wang, S.K. Gupta, Weighted random robust path delay testing of synthesized multilevel circuits, Proc. VLSI Test Symp., May 1994, pp. 291–297. Gaal, 1971 McWilliams, 1977 Berlekamp, 1968 Gill, 1966 Peterson, 1972 Golomb, 1982 Ronse, 1984, 16 C. Dufaza, Y. Zorian, On the generation of pseudo-deterministic two-patterns test sequence with LFSRs, Proc. Eur. Design Test Conf., 1997, 69–76.