The processing element design for a large-scale spatio-temporal pattern clustering system

The clustering of spatio-temporal patterns are essential for many applications. Established from the biological analogy of the cortex, the parametrically coupled logistic map network (PCLMN) provides a viable solution to the clustering problem. To engineer for a single-chip spatio-temporal pattern clustering system, the highly modular PCLMN is designed in analog circuit. In this paper, the 0.6 μm 5 V CMOS design of the processing element is presented. The analog design employs self-calibration techniques to improve the accuracy and robustness of the nonlinear circuits. A fabricated element covers a die area of 0.55 mm2, and consumes 240 mW power at 5 V supply. After calibration, simulation and testing results show that the element fulfills the system-level requirement of the Cort-X model for driving signals up to 1 MHz.