The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism)

Parallel Computing - Tập 31 - Trang 352-370 - 2005
Takashi Midorikawa1, Daisuke Shiraishi1, Masayoshi Shigeno1, Yasuki Tanabe1, Toshihiro Hanawa2, Hideharu Amano1
1Department of Information and Computer Science, Amano Lab, Keio University, 3-14-1 Hiyoshi, Kohoku-ku, Yokohama 223-8522, Japan
2Department of Information Technology, Tokyo University of Technology, Tokyo, Japan

Tài liệu tham khảo

Lawrie, 1975, Access and alignment of data in an array processor, IEEE Trans. Comput., c-24, 10.1109/T-C.1975.224157 Amano, 1992, SSS (simple serial synchronized)-MIN: a novel multistage interconnection architecture for multiprocessors, Proc. IFIP 12th World Computer Congress, I, 571 Hanawa, 1994, Multistage interconnection networks with multiple outlets, Proc. Int. Conf. Parallel Process., I, 1 Sasahara, 1994, SNAIL: a multiprocessor based on the simple serial synchronized multistage interconnection network architecture, Proc. Int. Conf. Parallel Process., I, 110 Yamamoto, 1999, Performance evaluation of SNAIL: a multiprocessor based on simple serial synchronized multistage interconnection network architecture, Parallel Comput., 25, 1081, 10.1016/S0167-8191(99)00038-1 Yamamoto, 1995, A preprocessing system of the EULASH: an environment for efficient use of multiprocessors with local memory, Proc. IASTED/ISMM Int. Conf. Parallel Distributed Comput. Syst., 68 Hanawa, 1997, MINC: multipstage interconnection network with Cache control mechanism, IEICE Trans. Informat. Syst., E80-D, 863 Iyer, 2000, Design and evaluation of a switch cache architecture for CC-NUMA multiprocessors, IEEE Trans. Comput., 49, 779, 10.1109/12.868025 Kamei, 1997, An LSI implemenation of the simple serial synchronized multistage interconnection network, Proc. Asian South Pacific Design Automation Conf., 671 Midorikawa, 1998, The MINC chip, Proc. Asian South Pacific Design Automation Conf., 337, 10.1109/ASPDAC.1998.669494 Kudoh, 1995, Hierarchical bit-map directory schemes on the RDT interconnection network for a massively parallel processor JUMP-1, Proc. Int. Conf. Parallel Process., I-186 H. Tanaka, The massively parallel processing system JUMP-1, IDS Press, ISBN 90-5199-262-9, 1996 Woo, 1995, The SPLASH-2 programs: characterization and methodological considerations, Proc. 22nd Int. Symp. Comput. Architect., 24, 10.1109/ISCA.1995.524546 Wakabayashi, 2000, Environment of multiprocessor simulator development, Proc. Int. Symp. Parallel Architect. Algorith. Networks, 64, 10.1109/ISPAN.2000.900263