Test-Per-Clock Logic BIST with Semi-Deterministic Test Patterns and Zero-Aliasing Compactor

Springer Science and Business Media LLC - Tập 20 Số 1 - Trang 109-122 - 2004
Ondřej Novák1, Zdeněk Plíva2, J. Nosek3, A. Hławiczka4, Tomasz Garbolino5, K. Gucwa6
1Technical University Liberec, Halkova 6, Liberec 1, Czech Republic. [email protected]#TAB#
2Technical University Liberec, Halkova 6, Liberec 1, Czech Republic. [email protected]#TAB#
3Technical University Liberec, Halkova 6, Liberec 1, Czech Republic. [email protected]#TAB#
4Silesian University of Technology, ul. Akademicka 16, Gliwice, Poland. [email protected]
5Silesian University of Technology, ul. Akademicka 16, Gliwice, Poland. [email protected]#TAB#
6Silesian University of Technology, ul. Akademicka 16, Gliwice, Poland. [email protected]

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Springer Science and Business Media LLC

Tập 20 Số 1

109-122

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