Synchronizability of distributed clock oscillators

H.-A. Tanaka1, A. Hasegawa2, H. Mizuno3, T. Endo4
1Department of Electronic Engineering, University of Electro-Communications, Tokyo, Japan
2Department of Electrical and Electronic Engineering, Gifu University, Gifu, Japan
3ULSI Research Department, Hitachi Central Research Laboratory Limited, Tokyo, Japan
4Department of Electronics and Communication, Meiji University, Kawasaki, Japan

Tóm tắt

We analyze the synchronizability of synchronous distributed oscillators (SDOs), a novel clocking scheme for microprocessors. A computer-aided perturbation analysis is developed for such systems, where analytically tractable equations of the clock phases are reduced from experimental data reflecting all circuit details. Using this reduction, a theory is constructed to explain the underlying mechanism of the synchronization in SDOs. It systematically explains the observed phenomena, the existence and stability of the (mutually) synchronized states, and the transition from the in-phase synchronized state to the out-of-phase (but still synchronized) state. Furthermore, the present theory of phase reduction provides a new design principle of coupled oscillators based on "the equation"; a precise delay control (less than the gate delay) circuit can be designed in a simple and general form.

Từ khóa

#Clocks #Frequency synchronization #Circuits #Equations #Voltage-controlled oscillators #Jitter #Delay #Distributed computing #Large scale integration #Threshold voltage

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