Study of Temperature Effect on Analog/RF and Linearity Performance of Dual Material Gate (DMG) Vertical Super-Thin Body (VSTB) FET
Tóm tắt
This work presents a simulation study of the influence of temperature on the performance of dual material gate (DMG) vertical super-thin body (VSTB) FET. The introduction of DMG causes a drop in the off-state current (Ioff) by ~99.18% and DIBL by 20%. Drop in the Ioff enhances the on-to-off current ratio (Ion/Ioff) by ~98.85%. A rigorous investigation on temperature dependency of DC, analog/RF, and linearity metrics was carried out. The zero temperature coefficient (ZTC) bias point for the DMG device was observed to be nearly at a gate bias of VG = 0.41 V. Various DC figures of merit (FoM) such as subthreshold swing (SS), Ion/Ioff, and threshold voltage (VT) show improvement with temperature fall. Lowering in temperature also leads to enhanced analog/RF performance by offering superior gm, gd, Cgg, Cgd, maximum fT, maximum GBP, intrinsic delay, TGF, TFP, GFP, and GTFP. However, linearity metrics like gm2, gm3, VIP2, VIP3, IIP3, IMD3, and 1-dB compression point show better performance with an increase in temperature.
Tài liệu tham khảo
Skotnicki T, Hutchby JA, Tsu-Jae K, Wong H-SP, Boeuf F (Jan.-Feb. 2005) The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance. IEEE Circuits and Devices Magazine 21(1):16–26. https://doi.org/10.1109/MCD.2005.1388765
Balestra F (2014) “Silicon-on-insulator devices,” Wiley Encyclopedia of Electrical and Electronics Engineering, 2014, Silicon-On-Insulator Devices
Jaju V, Dalal V (2004) "Silicon-on-insulator technology", EE 530 Advances in MOSFETs, pp. 1–12
Cristoloveanu S (Aug. 2001) Silicon on insulator technologies and devices: from present to future. Solid State Electron. 45(8):1403–1411
Zhang X, Connelly D, Takeuchi H, Hytha M, Mears RJ, Liu TK (2017) Comparison of SOI versus bulk FinFET technologies for 6T-SRAM voltage scaling at the 7−/8-nm node. IEEE Transactions on Electron Devices 64(1):329–332. https://doi.org/10.1109/TED.2016.2626397
Uchida K, Koga J and Takagi S (2003) "Experimental study on carrier transport mechanisms in double- and single-gate ultrathin-body MOSFETs - coulomb scattering, volume inversion, and δTSOI -induced scattering," IEEE International Electron Devices Meeting 2003, Washington, DC, USA, pp.33.5.1–33.5.4. doi: https://doi.org/10.1109/IEDM.2003.1269402
Omura Y, Konishi H, Yoshimoto K (2008) Impact of fin aspect ratio on short-channel control and drivability of multiple-gate SOI MOSFETs. J Semicond Technol Sci 8(4):302–310
Liu Y, Ishii K, Masahara M, Tsutsumi T, Takashima H, Yamauchi H, and Suzuki E (2004) “Cross-sectional channel shape dependence of short channel effects in fin-type double-gate metal oxide semiconductor field effect transistors,” Jpn. J. Appl. Phys., vol. 43, no. 4S, p. 2151
Koldiaev V and Pirogova R (2014) “Vertical super-thin body semiconductor on dielectric wall devices and methods of their fabrication,” U.S. Patent 8 796 085 B2
Roy S, Chatterjee A, Sinha DK, Pirogova R, Baishya S (May 2017) 2-D analytical modeling of surface potential and threshold voltage for vertical super-thin body FET. IEEE Transactions on Electron Devices 64(5):2106–2112. https://doi.org/10.1109/TED.2017.2687465
Maity NP, Maity R, Maity S, and Baishya S (2019) “Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation,” Journal of Computational Electronics
Krzeminski CD (2012) "Stress mapping in strain-engineered silicon p-type MOSFET device: A comparison between process simulation and experiments", J. Vac. Sci. Technol. B, vol. 30, no. 2, pp. 022203
R. T. Bühler et al., "TCAD strain calibration versus Nanobeam diffraction of source/drain stressors for Ge MOSFETs," in IEEE Transactions on Electron Devices, vol.62, no.4, pp.1079–1084, April2015. doi: https://doi.org/10.1109/TED.2015.2397441
A. Khakifirooz et al., "Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS", Proc. Symp. VLSI Technol. (VLSIT), pp. 117–118, Jun. 2012
Xu N, Ho B, Choi M, Moroz V, Liu T-JK (2012) Effectiveness of stressors in aggressively scaled FinFETs. IEEE Trans. Electron Devices 59(6):1592–1598
Morvan S et al (Jun. 2012) Efficiency of mechanical stressors in planar FDSOI n and p MOSFETs down to 14 nm gate length. Proc Symp VLSI Technol:111–112
Smith L, Moroz V, Eneman G, Verheyen P, Nouri F, Washington L, Jurczak M, Penzin O, Pramanik D, de Meyer K (Sep. 2005) Exploring the limits of stress-enhanced hole mobility. IEEE Electron Device Lett 26(9):652–654
Chidambaram PR, Bowen C, Chakravarthi S, Machala C, Wise R (May 2006) Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing. IEEE Trans Electron Devices 53(5):944–964
Ding Y, Cheng R, Du A, Yeo YC (2013) " Lattice strain analysis of silicon fin field-effect transistor structures wrapped by Ge 2 Sb 2 Te 5 liner stressor ", J. Appl. Phys., vol. 113, no. 7, pp. 073708–1–073708-8
Chen X, Tan CM (July 2014) Modeling and analysis of gate-all-around silicon nanowire FET. Microelectron Reliab 54:1103–1108
Chen J et al. (1991) "Interface quality of SOI MOSFET's reflected in noise and mobility," 1991 IEEE International SOI Conference Proceedings, Vail Valley, CO, USA, pp. 100–101. doi: https://doi.org/10.1109/SOI.1991.162876
Reimbold G (1984) Modified 1/f trapping noise theory and experiments in MOS transistors biased from weak to strong inversion—influence of interface states. IEEE Trans. Electron Devices ED-31:1190
Kim S, Jo M, Jung S, Choi H, Lee J, Chang M, Cho C, Hwang H (2011) Improvement of interface quality by post-annealing on silicon nanowire MOSFET devices with multi-wire channels. Microelectron Eng 88:273–275
Nayfeh A, Chui CO, Yonehara T, Saraswat KC (2005) Fabrication of high-quality p-MOSFET in Ge grown heteroepitaxially on Si. IEEE Electron Device Letters 26(5):311–313
Mohapatra SK, Pradhan KP, Sahu PK (Feb. 2015) Temperature dependence inflection point in ultra-thin Si directly on insulator (SDOI) MOSFETs: an influence to key performance metrics. Superlattice Microst 78:134–143
Hashim Y, "Temperature effect on ON/OFF current ratio of FinFET transistor," 2017 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), Batu Ferringhi, 2017, pp. 231–234
Diab A, Torres Sevilla GA, Cristoloveanu S, Hussain MM (2014) Room to high temperature measurements of flexible SOI FinFETs with Sub-20-nm fins. IEEE Transactions on Electron Devices 61(12):3978–3984. https://doi.org/10.1109/TED.2014.2360659
Y. Hashim, O. Sidek, "Temperature effect on IV characteristics of Si nanowire transistor", IEEE Colloquium on Humanities Science and Engineering (CHUSER), pp. 331–334, 2011
Hashim Y, Sidek O (2012) Effect of temperature on the characteristics of silicon nanowire transistor. J Nanosci Nanotechnol 12(10):7849–7852
Maity NP, Maity R, Baishya S (November 2017) Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO2 based MOS devices. Superlattice Microst 111:628–641
Maity NP, Maity R, Thapa R, Baishya S (July 2016) A tunneling current density model for ultra thin hfo2 high-k dielectric material based MOS devices. Superlattice Microst 95:24–32
Maity NP, Maity R, Dutta S, Deb S, Sravani KG, Rao KS, and Baishya S (2020) “Effects of hafnium oxide on surface potential and drain current models for subthreshold Short Channel metal–oxide–semiconductor-field-effect-transistor,” Transactions on Electrical and Electronic Materials, 1–9
Maity NP, Maity R, Baishya S (2019) An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET. J Comput Electron 18:65–75. https://doi.org/10.1007/s10825-018-1279-5
Maity NP, Maity R, Maity S, Baishya S (2019) A New Surface Potential and Drain Current Model of Dual Material Gate Short Channel Metal Oxide Semiconductor Field Effect Transistor in Sub-Threshold Regime: Application to High-k Material HfO2. Journal of Nanoelectronics and Optoelectronics 14:868–876
J. -P. Raskin, Tsung Ming Chung, V. Kilchytska, D. Lederer and D. Flandre, "Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization," IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1088–1095, May2006. doi: https://doi.org/10.1109/TED.2006.871876
Eminente S, Alessandrini M, Fiegna C (2004) Comparative analysis of the RF and noise performance of bulk and single-gate ultrathin SOI MOSFETs by numerical simulation. Solid State Electron 48(4):543–549
Kilchytska V, Nève A, Vancaillie L, Levacq D, Adriaensen S, van Meer H, De Meyer K, Raynaud C, Dehan M, Raskin J-P, Flandre D (Mar. 2003) Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Trans. Electron Devices 50(3):577–588
Goswami R, Bhowmick B, Baishya S (October 2015) Electrical noise in circular gate tunnel FET in presence of interface traps. Superlattice Microst 86:342–354
Vijayvargiya V, Vishvakarma SK (2014) Effect of drain doping profile on double-gate tunnel field-effect transistor and its influence on device RF performance. in IEEE Transactions on Nanotechnology 13(5):974–981. https://doi.org/10.1109/TNANO.2014.2336812
Ghosh P, Haldar S, Gupta RS, Gupta M (2012) An investigation of linearity performance and intermodulation distortion of GME CGT MOSFET for RFIC design. IEEE Transactions on Electron Devices 59(12):3263–3268. https://doi.org/10.1109/TED.2012.2219537
Saha R, Bhowmick B, Baishya S (2018) Temperature effect on RF/analog and linearity parameters in DMG FinFET. Applied Physics A 124:642. https://doi.org/10.1007/s00339-018-2068-5
Murmann B, Nikaeen P, Connelly DJ, Dutton RW (2006) Impact of scaling on analog performance and associated modeling needs. in IEEE Transactions on Electron Devices 53(9):2160–2167. https://doi.org/10.1109/TED.2006.880372
Kranti A, Armstrong GA (2010) Nonclassical Channel design in MOSFETs for improving OTA gain-bandwidth trade-off. IEEE Transactions on Circuits and Systems I: Regular Papers 57(12):3048–3054. https://doi.org/10.1109/TCSI.2010.2071470
Sahu PK, Mohapatra SK, Pradhan KP (2014) Impact of downscaling on analog/RF performance of sub-100 nm GS-DG MOSFET. J Microelectron Electron Components Mater 44(2):119–125
S. K. Mohapatra, K. P. Pradhan, D. Singh and P. K. Sahu, "The role of geometry parameters and fin aspect ratio of sub-20nm SOI-FinFET: an analysis towards analog and RF circuit design," IEEE Transactions on Nanotechnology, vol.14, no.3, pp.546–554, May2015. doi: https://doi.org/10.1109/TNANO.2015.2415555
Niu G, Liang Q, Cressler JD, Webster CS, Harame DL (Sept. 2001) RF linearity characteristics of SiGe HBTs. IEEE Transactions on Microwave Theory and Techniques 49(9):1558–1565. https://doi.org/10.1109/22.942567
Filanovsky IM and Najafizadeh L, "Zeroing in on a zero-temperature coefficient point" Proc. 45th Midwest Symp. Circuits Syst. vol. 1 pp. 271–274 2002-Aug.
Kanda K, Nose K, Kawaguchi H, Sakurai T (2001) Design impact of positive temperature dependence on drain current in sub-I-V CMOS VLSIs. IEEE J SolidState Circuits 36(10):1559–1564
Filanovsky IM, Allam A (2001) "mutual compensation of mobility and threshold voltage temperature effects with application in CMOS circuits" IEEE trans. Circ Syst pt I: Fundam Theory Applic 48(7):876–884
Filanovsky IM, Su AA and Lim T "Temperature dependence of output voltage generated by interaction of threshold voltage and mobility of NMOS transistor" Analog Integrated Circuits and Signal Processing vol. 27 no. 3 pp. 229–238 2001
Clark RD (2014) Emerging applications for high-K materials in VLSI technology. Materials 7:2913–2944
Hall S, Buiu O, Mitrovic IZ, Lu Y, Davey WM (2007) Review and perspective of high-k dielectrics on silicon. J Telecomm Info Technol 2:33–43
Wang B, Huang W, Chi L, Al-Hashimi M, Marks TJ, Facchetti A (2018) High-k gate dielectrics for emerging flexible and stretchable electronics. Chem Rev 118:5690–5754
Lee BH, Song SC, Choi R, Kirsch P (Jan. 2008) Metal electrode/high-k dielectric gate-stack Technology for Power Management. IEEE Transactions on Electron Devices 55(1):8–20. https://doi.org/10.1109/TED.2007.911044
Ribes G, Mitard J, Denais M, Bruyere S, Monsieur F, Parthasarathy C, Vincent E, Ghibaudo G (March 2005) Review on high-k dielectrics reliability issues. IEEE Transactions on Device and Materials Reliability 5(1):5–19. https://doi.org/10.1109/TDMR.2005.845236
Sentaurus Device User Manual, Version J 2014.09, Synopsis Inc., Mountain View, CA, USA, Sep. 2014
Long W, Ou H, Kuo J, Chin KK (1999) Dual-material gate (DMG) field effect transistor. in IEEE Transactions on Electron Devices 46(5):865–870. https://doi.org/10.1109/16.760391
Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Transactions on Device and Materials Reliability 4(1):99–109. https://doi.org/10.1109/TDMR.2004.82435
Zhou X (Jan. 2000) Exploring the novel characteristics of hetero-material gate field-effect transistors (HMGFETs) with gate-material engineering. in IEEE Transactions on Electron Devices 47(1):113–120. https://doi.org/10.1109/16.817576
Osman AA, Osman MA, Dogan NS, Iman MA (September 1995) Zero-temperature-coefficient biasing point of partially depleted SOI MOSFET's. IEEE Transactions on Electronic Devices 42(9):1709–1711
Jeon DS, Burk DE (1991) A temperature-dependent SOI MOSFET model for high-temperature application. (27-300 C). IEEE Transactions on Electronic Devices 38(9):2101–2110
Sharma RK, Antonopoulos A, Mavredakis N and Bucher M (2012) "analog/RF figures of merit of advanced DG MOSFETs," 2012 8th International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Playa del Carmen, pp. 1-4. doi: https://doi.org/10.1109/ICCDCS.2012.6188900
Fouzy BBA, Reaz MBI, Bhuiyan MAS, Badal MTI and Hashim FH, "Design of a low-power high-speed comparator in 0.13μm CMOS," 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES), Putrajaya, 2016, pp. 289–292. doi: https://doi.org/10.1109/ICAEES.2016.7888054