Scalable Gaussian Normal Basis Multipliers over GF(2 m ) Using Hankel Matrix-Vector Representation

Denning, D. E. R. (1983). Cryptography and data security. Reading: Addison-Wesley.

Rhee, M. Y. (1994). Cryptography and secure communications. Singapore: McGraw-Hill.

Menezes, A., Oorschot, P. V., & Vanstone, S. (1997). Handbook of applied cryptography. Boca Raton: CRC Press.

Omura, J. K., & Massey, J. L. (1986). Computational method and apparatus for finite field arithmetic. U.S. Patent Number 4,587,627, May.

Reyhani-Masoleh, A., & Hasan, M. A. (2005). Low complexity word-level sequential normal basis multipliers. IEEE Trans Computers, 54(2), Feb.

Lee, C. Y., & Chang, C. J. (2004). Low-complexity linear array multiplier for normal basis of type-II. IEEE Intern Conf Multimedia and Expo, 3, 1515–1518.

Lee, C. Y., Lu, E. H., & Lee, J. Y. (2001). Bit-parallel systolic multipliers for GF(2 m ) fields defined by all-one and equally-spaced polynomials. IEEE Trans Computers, 50(5), 385–393.

Hasan, M. A., Wang, M. Z., & Bhargava, V. K. (1993). A modified Massey-Omura parallel multiplier for a class of finite fields. IEEE Trans Computers, 42(10), 1278–1280.

Kwon, S. (2003). A low complexity and a low latency bit parallel systolic multiplier over GF(2 m ) using an optimal normal basis of type II. Proc. of 16th IEEE Symp. Computer Arithmetic, pp. 196–202, June.

Lee, C. Y., & Chiou, C. W. (2005). Design of low-complexity bit-parallel systolic Hankel multipliers to implement multiplication in normal and dual bases of GF(2 m ). IEICE Trans Fund, E88-A(11), 3169–3179.

IEEE Standard 1363-2000, IEEE Standard Specifications for Public-Key Cryptography. Jan. 2000.

National Inst. of Standards and Technology, Digital Signature Standard, FIPS Publication 186-2, Jan. 2000.

Reyhani-Masoleh, A. (2006). Efficient algorithms and architectures for field multiplication using Gaussian normal bases. IEEE Trans Computers, 55(1), 34–47.

Lee, C. Y. (2003). Low-latency bit-parallel systolic multiplier for irreducible x m + x n + 1 with gcd(m, n)=1. IEICE Trans Fund, E86-A(11), 2844–2852.

Lee, C. Y., Horng, J. S., & Jou, I. C. (2005). Low-complexity bit-parallel systolic Montgomery multipliers for special classes of GF(2 m ). IEEE Trans Computers, 54(9), 1061–1070.

Lee, C. Y. (2005). Systolic architectures for computing exponentiation and multiplication over GF(2 m ) using polynomial ring basis. Journal of LungHwa University, 19, 87–98.

Lee, C. Y. (2003). Low complexity bit-parallel systolic multiplier over GF(2 m ) using irreducible trinomials. IEE Proc-Comput and Digit Tech, 150, 39–42.

Paar, C., Fleischmann, P., & Soria-Rodriguez, P. (1999). Fast arithmetic for public-key algorithms in Galois fields with composite exponents. IEEE Trans Computers, 48(10), 1025–1034.

Kim, N. Y., & Yoo, K. Y. (2005). Digit-serial AB2 systolic architecture in GF(2 m ). IEE Proc Circuits Devices Systems, 152(6), 608–614.

Kang, S. M., & Leblebici, Y. (1999). CMOS digital integrated circuits analysis and design. McGraw-Hill.

Logic selection guide: STMicroelectronics < http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00000249.pdf >.

Logic selection guide: STMicroelectronics < http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00000294.pdf >.

Logic selection guide: STMicroelectronics < http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00002627.pdf >.

Logic selection guide: STMicroelectronics < http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00000351.pdf >.

Kim, C. H., Hong, C. P., & Kwon, S. (2005). A digit-serial multiplier for finite field GF(2 m ). IEEE Trans VLSI, 13(4), 476–483.

Guo, J. H., & Wang, C. L. (1998). Digit-serial systolic multiplier for finite fields GF(2 m ). IEE Proc-Comput Digit Tech, 145(2), 143–148.

Kung, S. Y. (1988). VLSI array processors. Englewood Cliffs: Prentice-Hall.

Wu, H., Hasan, M. A., Blake, I. F., & Gao, S. (2002). Finite field multiplier using redundant representation. IEEE Trans Computers, 51(11), 1306–1316.

Mullin, R. C., Onyszchuk, I. M., Vanstone, S. A., & Wilson, R. M. Optimal Normal Bases in GF(p n ). Discrete Applied Math, 22, 149–161, 1988/1989.

Reyhani-Masoleh, A., & Hasan, M. A. (2003). Fast normal basis multiplication using general purpose processors. IEEE Trans Computers, 52(11), 1379–1390.

Song, L., & Parhi, K. K. (1998). Low-energy digit-serial/parallel finite field multipliers. Journal of VLSI Signal Processing, 19, 149–166.

Tenca, A. F., & Koc, C. K. (1999). A scalable architecture for Montgomery multiplication. Proceedings of Cryptographic Hardware and Embedded System (CHES 1999), No. 1717 in Lecture Notes in Computer Science, pp. 94–108, Springer-Verlag.

Reyhani-Masoleh, A., & Hasan, M. A. (2002). Efficient digit-serial normal basis multipliers over GF(2 M ). IEEE Intern. Conf., ISCAS.

Fan, H., & Hasan, M. A. (2007). A new approach to subquadratic space complexity parallel multipliers for extended binary fields. IEEE Trans Computers, 56(2), 224–233.

Fan, H., & Hasan, M. A. (2007). Subquadratic computational complexity schemes for extended binary field multiplication using optimal normal bases. IEEE Trans Computers, 56(10), 1435–1437.

Chiou, C. W., Chang, C. C., Lee, C. Y., Lin, J. M., & Hou, T. W. (2009). Concurrent error detection and correction in Gaussian normal basis multiplier over GF(2m). IEEE Trans Computers, 58(6), 851–857.