SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement
Tóm tắt
Silicon debugging of integrated circuits is exacerbated by the lack of golden responses, highly restricted observability and irreproducible nature of bugs. Debug engineers need to develop better methods that can assist in error localization at lower level(netlist) granularity. It is widely accepted that root-cause analysis of electrical bugs is highly difficult which further elongates the time needed to fix them. This paper revisits methodologies to debug electrical errors through satisfiability(SAT) solving under a limited visibility environment. We propose various SAT formulations and analyze their efficacy in error localization for a variety of benchmark circuits. The selection of debugging instrumentation is an important issue in post-silicon validation. We analyze different graph-based signal tracing techniques and propose a methodology that utilizes clustering of the nodes of the circuit graph. We aim at minimizing the overhead associated with signal tracing while maintaining the error localization efficacy. We address scalability concerns in SAT solving through partitioning of large error traces. We provide localization results on two different error models (bit-flip and stuck-at) and evaluate its efficiency through a set of different metrics.
Tài liệu tham khảo
Basu K, Mishra P, Patra P, Nahir A, Adir A (2013) Dynamic selection of trace signals for post-silicon debug. In: Proc 14th International Workshop on Microprocessor Test and Verification, pp 62–67
Yang JS, Touba NA (2008) Enhancing silicon debug via periodic monitoring. In: Proc 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp 125–133
Zhu CS, Weissenbacher G, Malik S (2011) Post-silicon fault localisation using maximum satisfiability and backbones. In: Proc International Conference on Formal Methods in Computer-Aided Design, FMCAD ’11, Austin, USA, October 30 - November 02, 2011, pp 63–66
Prabhakar S, Hsiao MS (2010) Multiplexed trace signal selection using non-trivial implication-based correlation. In: 2010 11th International Symposium on Proc Quality Electronic Design (ISQED), pp 697–704
Li M, Davoodi A (2013) A hybrid approach for fast and accurate trace signal selection for post-silicon debug. In: Proc Design, Automation Test in Europe Conference Exhibition (DATE) 2013, pp 485–490
Suelflow A, Fey G, Bloem R, Drechsler R (May 2008) Using unsatisfiable cores to debug multiple design errors, In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI, GLSVLSI ’08, pp 77–82
Yang YS, Veneris A, Nicolici N, Fujita M (2012) Automated data analysis techniques for a modern silicon debug environment. In: Proc 17th Asia and South Pacific Design Automation Conference, pp 298–303
Zhu CS, Weissenbacher G, Malik S, backbones Silicon fault diagnosis using sequence interpolation with. In: Proc. The IEEE/ACM International Conference on Computer-Aided Design ICCAD 2014 (2014)
Biere A Picosat essentials. Journal on Satisfiability, Boolean Modeling and Computation (JSAT, p. 2008)
http://www.opencores.org/
Taatizadeh P, Nicolici N (2016) Automated selection of assertions for bit-flip detection during post-silicon validation. IEEE Trans Comput Aided Des Integr Circuits Syst 35(12):2118– 2130
Kumar B, Basu K, Jindal A, Fujita M, Singh V (2017) Improving post-silicon error detection with topological selection of trace signals. In: Proc 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp 1–6
Basu K, Mishra P (2013) Rats: Restoration-aware trace signal selection for post-silicon validation. IEEE Trans Very Large Scale Integr VLSI Syst 21(4):605–613
Rahmani K, Mishra P, Ray S (2014) Efficient trace signal selection using augmentation and ilp techniques. In: Proc Fifteenth International Symposium on Quality Electronic Design, pp 148–155
Pal D, Ma S, Vasudevan S (2018) Emphasizing functional relevance over state restoration in post-silicon signal tracing. In: Proc IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 1–1
Ko HF, Nicolici N (2010) Automated trace signals selection using the rtl descriptions. In: Proc IEEE International Test Conference, pp 1–10
Kumar B, Jindal A, Singh V, Fujita M (2017) A methodology for trace signal selection to improve error detection in post-silicon validation. In: Proc 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems(VLSID), pp 147–152
Li M, Davoodi A (Jan 2014) Multi-mode trace signal selection for post-silicon debug. In: Proc 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp 640–645
Kumar B, Basu K, Fujita M, Singh V (2018) Post-silicon gate-level error localization with effective amp;amp; combined trace signal selection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 1–1
Basu K, Mishra P, Patra P (2011) Efficient combination of trace and scan signals for post silicon validation and debug. In: Proc 2011 IEEE International Test Conference, pp 1–8
Vali A, Nicolici N (2018) Bit-flip detection-driven selection of trace signals. IEEE Trans Comput Aided Des Integr Circuits Syst 37(5):1076–1089
Kumar B, Jindal A, Fujita M, Singh V (2017) Post-silicon observability enhancement with topology based trace signal selection. In: Proc 2017 18th IEEE Latin American Test Symposium (LATS), pp 1–6
Rahmani K, Proch S, Mishra P (2016) Efficient selection of trace and scan signals for post-silicon debug. IEEE Trans Very Large Scale Integr VLSI Syst 24(1):313–323
Liu X, Xu Q (2012) On signal selection for visibility enhancement in trace-based post-silicon validation. IEEE Trans Comput Aided Des Integr Circuits Syst 31(8):1263–1274
Hung E, Wilton SJE (2013) Scalable signal selection for post-silicon debug. IEEE Trans Very Large Scale Integr VLSI Syst 21(6):1103–1115
BeigMohammadi S, Alizadeh B (2016) Combinational trace signal selection with improved state restoration for post-silicon debug. In: Proc 2016 Design Automation Test in Europe Conference Exhibition (DATE), pp 1369–1374
Iwata K, Gharehbaghi AM, Tahoori MB, Fujita M (2017) Post silicon debugging of electrical bugs using trace buffers. In: Proc 2017 IEEE 26th Asian Test Symposium (ATS), pp 189–194
Kumar B, Fujita M, Singh V (2019) A methodology for sat-based electrical error debugging during post-silicon validation. In: Proc 2019 32nd International Conference on VLSI Design(VLSID), pp 389–394
Park SB, Mitra S (2008) Ifra: Instruction footprint recording and analysis for post-silicon bug localization in processors. In: Proc Design Automation Conference, 2008. DAC 2008, 45th ACM/IEEE, pp 373–378
Kumar B, Jindal A, Fujita M, Singh V (2017) Combining restorability and error detection ability for effective trace signal selection. In: Proceedings of the on Great Lakes Symposium on VLSI 2017, pp 191–196
Sabaghian-Bidgoli H, Behnam P, Alizadeh B, Navabi Z (2017) Reducing search space for fault diagnosis: A probability-based scoring approach. In: Proc 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp 545–550
Hong T, Li Y, Park SB, Mui D, Lin D, Kaleq ZA, Hakim N, Naeimi H, Gardner DS, Mitra S (2010) Qed: Quick error detection tests for effective post-silicon validation. In: Proc 2010 IEEE International Test Conference, pp 1–10