Rapid prototyping for wireless designs: the five-ones approach

Signal Processing - Tập 83 - Trang 1427-1444 - 2003
Markus Rupp1, Andreas Burg2, Eric Beck3
1TU Wien, Gusshausstr 25/389, Vienna 1040, Austria
2ETH-Zurich, Integrated Systems Laboratory, Gloriastr. 35, CH-8092 Zurich, Switzerland
3Bell-Labs, Lucent Technologies, Wireless Research Laboratory, 791 Holmdel-Keyport Road, Holmdel, NJ 07733-0400, USA

Tài liệu tham khảo

A. Adjoudani, E. Beck, A. Burg, G.M. Djuknic, T. Gvoth, D. Haessig, S. Manji, M. Milbrodt, M. Rupp, D. Samardzija, A. Siegel, T. Sizer II, C. Tran, S. Walker, S.A. Wilkus, P. Wolniansky, Prototype experience for MIMO BLAST over third generation wireless system, Special Issue JSAC on MIMO Systems, 21 (April 2003) 440–451. A|RT Builder, A|RT Designer, and A|RT Library are trademarks of ADELANTE TECHNOLOGIES, http://www.adelantetech.com. Baines, 1995, The DSP bottleneck, IEEE Comm. Mag., 33, 46, 10.1109/35.392999 R. Baines, D. Pulley, A total cost approach to evaluating different reconfigurable architectures for baseband processing in wireless receivers, IEEE Comm. Mag. 41 (1) (January 2003) 105–113. Y. Baltaci, I. Kaya, A. Nix, Implementation of a HiperLAN/1 compatible CMF-DFE equaliser, Proceedings of VTC, 2000, p. 1884. T. Blickle, J. Teich, L. Thiele, System-level synthesis using evolutionary algorithms, Design Automat. Embedded Systems (1) (1998) 1–40. U. Bortfeld, C. Mielenz, White paper C++ system simulation interfaces, Infineon, July 16, 2000. R.W. Brodersen, W.R. Davis, D. Yee, N. Zhang, Wireless systems-on-a-chip design, in: Proceedings of the International Symposium on VLSI Technology, Systems, and Applications, Hsinchu, Taiwan, April 2001, pp. 45–48. A. Burg, M. Guillaud, M. Rupp, E. Beck, D. Perels, N. Felber, W. Fichtner, FPGA implementation of a MIMO receiver front-end for UMTS, Proceedings of the Zürich Seminar, February 2002, pp. 8_1–8_6. A. Burg, B. Haller, M. Guillaud, M. Rupp, E. Beck, L. Mailaender, A rapid prototyping methodology for algorithm development in wireless communications, in: Proceedings of Design, Automation and Test in Europe DATE’01, Munich, 13–16 March, 2001. Design Compiler and COSSAP/CoCentric System Studio are trademarks of SYNOPSYS INC., http://www.synopsys.com. G.J. Foschini, M.J. Gans, On limits of wireless communications in a fading environment when using multiple antenna, Wireless Personal Comm. (6) (1998) 315–335. J. Gleick, A bug and a crash, http://www.around.com/ariane.html. Golden, 1999, Detection algorithm and initial laboratory results using V-BLAST space-time communication architecture, Electron. Lett., 35, 11, 10.1049/el:19990058 M. Guillaud, A. Burg, L. Mailaender, B. Haller, M. Rupp, E. Beck, From basic concept to real-time implementation: prototyping WCDMA downlink receiver algorithms—a case study, Proceedings of 34rd Asilomar Conference, Monterey, CA, October 2000, pp. 84–88. M. Guillaud, S. Das, A. Burg, M. Rupp, E. Beck, Rapid prototyping design of a 4×4 BLAST-over-UMTS receiver, Proceedings of the 35th Asilomar Conference, Monterey, CA, November 2001, pp. 1256–1260. A. Hoffmann, T. Kogel, H. Meyr, A framework for fast hardware–software co-simulation, in: Proceedings of Design, Automation and Test in Europe DATE’01, Munich, 13–16 March, 2001, pp. 760–764. http://www.rational.com/products/clearcase/index.jsp. http://www.upv.es/cost259/right.htm. http://download.cyclic.com/pub/. http://www.proxim.com. http://www.systemc.org. Jakes, 1974 Janka, 2002 B. Jones, S. Rajagopal, J. Cavallaro, Real-time DSP multiprocessor implementation for future wireless base-station receivers, TI DSPS Fest, Wireless Applications, TX, August 3, 2000. A. Klauser, Trends in high-performance microprocessor design, Telematik (1) (2001) 12–21. W. Mueller, J. Ruf, D. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl, The simulation semantics of systemC, in: Proceedings of Design Automation and Test in Europe, DATE’2001, Munich, 13–16 March, 2001, pp. 64–70. N2C is a trademark of CoWare, http://www.coware.com. J. Nikolic-Popovic, Application of Texas Instruments’ TMS320C6400 in 3G wireless infrastructure transceivers, Proceedings of the Ninth Signal Processing Workshop, Hunt, TX, October 2000. O. Ogawa, K. Takagi, Y. Itoh, S. Kimura, K. Watanabe, Hardware synthesis from C programs with estimation of bit length of variables, IEICE Trans. Fund. E82-A (11) (November 1999) 2338–2347. V.N. Patel, C.K. Wiese, F.M. Hiemstra, S.C. Himes, Rapid development and commercialization of products-A business imperative in the global telecommunication landscape, Bell Labs Technical J. 5 (4) (October–December 2000) 157–171. M. Rupp, A 64-point FFT design example using A|RT-designer, Proceedings of the 34rd Asilomar Conference, Monterey, CA, October 2000, pp. 389–393. M. Rupp, On the impact of uncertainties in iterative MIMO decoding, Proceedings of the 36th Asilomar Conference, Monterey, CA, November 2002. M. Rupp, E. Beck, R. Krishnamoorthy, Rapid prototyping for a high data rate wireless local loop, Proceedings of the 33rd Asilomar Conference, Monterey, CA, October 1999, pp. 993–997. M. Rupp, M. Guillaud, S. Das, On MIMO decoding algorithms for UMTS, Proceedings of the 35th Asilomar Conference, Monterey, CA, November 2001, pp. 975–979. Seskar, 1999, A software radio architecture for linear multiuser detection, IEEE J. Selected Areas Comm., 17, 814, 10.1109/49.768197 SIMULINK is a trademark of MATHWORKS, http://www.mathworks.com-1888, 2000. SPW is a trademark of CADENCE CORPORATION, http://www.cadence.com. S. Srikanteswara, J.H. Reed, P. Athanas, R. Boyle, A soft radio architecture for reconfigurable platforms, IEEE Comm. Mag. 38 (2) (February 2000) 140–147. Y. Sun, A.R. Nix, D.R. Bull, D. Milford, H. de Beauchesne, R. Sperling, Ph. Rouzet, Design of a novel delayed feedback equaliser for HiperLAN/1 FPGA implementation, VTC 1999, pp. 300–304. Sundance is a trademark of SUNDANCE MULTIPROCESSOR TECHNOLOGY LTD. & SUNDANCE DSP INC., http://www.sundance.com. V. Sundaramurthy, J.R. Cavallaro, A software simulation testbed for third generation CDMA wireless systems, in: Proceedings of the Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, October 1999, pp. 1680–1684. TI TMS320C6000 DSP Platform http://www.ti.com/sc/docs/products/dsp/c6000/index.htm. UMTS-Standard: TS 125.211, TS 125.213, ETSI, http://www.3gpp.org. Virtex and ChipScope are trademarks of XILINX INC, http://www.xilinx.com. VISUAL ELITE is a trademark of INNOVENDA, http://www.innoveda.com/products/datasheets_HTML/visualelite.asp. J.S. Wang, P.L. Lin, W.H. Sheen, D. Sheng, Y.M. Huang, A compact adaptive equalizer IC for Hiperlan system, ISCAS 2000, Switzerland, May 2000, pp. II265–268. P.W. Wolniansky, G.J. Foschini, G.D. Golden, R.A. Valenzuela, V-BLAST: an architecture for achieving very high data rates over rich-scattering wireless channels, in: Proceedings of the ISSSE-98, Pisa, Italy, 1998, pp. 295–300.