Panovic, M., & Demosthenous, A. (2005). A low power block-matching analog motion estimation processor. In IEEE international symposium on circuits and systems, (Vol. 5, pp. 4827–4830).
Porto, M., Bampi, S., Susin, A., & Agostini L. (2008, September). Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV. 21st symposium on integrated circuits and systems design (pp. 216–221).
Weinberger, A. (1981). 4-2 Carry-Save Adder Module. IBM Technical Disclosure Bulletin.
Oklobdzija, V., Villeger, D., & Liu, S. (1996). A method for speed optimized partial product reduction and generation of fast parallel multipliers and algorithmic approach. IEEE Transaction on Computers, 45(3), 294–306.
Chang, C. H., Gu, J., & Zhang, M. (2004). Ultra low-voltage low-power COMS 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Transaction on Circuits and Systems-I, 51(10), 1985–1997.
Rouholamini, M., Kavehie, O., Mirbaha, A., Jasbi, S., & Navi, K. (2007). A new design for 7:2 compressors. In IEEE/ACS International Conference on Computer Systems and Applications.
Yang, H., Wolf, W., & Vijaykrishnan, N. (2005). Power and performance analysis of motion estimation based on hardware and software realizations. IEEE Transactions on Computers, 54(6), 714–726.
Kalaycioglu, C., Ulusel, O., & Hamzaoglu, I. (2009). Low power techniques for motion estimation hardware. International conference on field programmable logic and applications, FPL 2009 (pp. 180–185).
Murachi, Y., Matsuno, T., Hamano, K., Miyakoshi, J., Miyama, M., & Yoshimoto M. (2005). A 95mW MPEG2 MP@HL motion estimation processor core for portable high resolution video application. In Symposium on VLSI Circuits Digest of Technical Papers, (pp. 212–215).
Cheng, H-Wen, & Dung, L-Rong. (2004). A vario-power ME architecture using content-based subsample algorithm. IEEE Transactions on Consumer Electronics, 50, 349–354.
Miyama, M., Miyakoshi, J., Kuroda, Y., Imamura, K., Hashimoto, H., & Yoshimoto, M. (2004). A sub-mW MPEG-4 motion estimation processor core for mobile video application. IEEE Journal of Solid-State Circuits, 30(9), 1562–1570.
Wang, S-Hao, Tai, S-Hsin, & Chiang, T. (2009). A low-power and bandwidth-efficient motion estimation IP core design using binary search. IEEE Transactions on Circuits and Systems for Video Technology, 19(5), 760–765.
Chen, Y-Han, Chen, T-Chien, Tsai, C-Yung, Tsai, S-Fang, & Chen, L-Gee. (2008). Data reuse exploration for low power motion estimation architecture design in H.264 encoder. Journal of Signal Processing Systems, 50, 1–17.
Hishan, C., Komal, K., & Mishra, A. (2009). Low power and less area architecture for integer motion estimation. International Journal of Electronics, Circuits and Systems, 3(1), 11–17.
Liu, Z., Song, Y., Shao, M., Li, S., Li, L., Got, S., & Ikenaga, T. (2007). 32-parallel sad tree hardwired engine for variable block size motion estimation in HDTV1080p real-time encoding application. In IEEE workshop on signal processing systems (pp. 675–680).
Huang, Y., Liu, Q., & Ikenaga, T. (2008). Compressor tree based processing element optimization in propagate partial SAD architecture. In IEEE Asia Pacific conference on circuits and systems (pp. 1786–1789).
Huang, Y., et al. (2008). Parallel improved HDTV720p targeted propagate partial SAD architecture for variable block size motion estimation in H.264/AVC. IEICE Transactions on Fundamentals, E91-A(4), 987–997.
Huang, Y., Liu, Q., & Ikenaga, T. (2009). Content aware configurable architecture for H.264/AVC integer motion estimation engien. In IEEE international conference on multimedia and expo (pp. 37–40).
Tham, J., Ranganath, S., Ranganath, M., & Kassim, A. (1998). A novel unrestricted center-biased diamond search algorithm for block motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 8(4), 369–375.
Veeramachaneni, S., Krishna, K., Avinash, L., Puppala, S., & Srinivas, M. (2007). Novel architectures for high-speed and low-power 3-2. 4-2 and 5-2 compressors. In 20th international conference on VLSI design (VLSID’ 07).
Warrington, S., Chan, W., & Sudharsanan, Subramania (2006). Scalable high-throughput architecture for H.264/avc variable block size motion estimation, In international symposium on circuits and systems, 2006. ISCAS.
Ndili, O., & Ogunfunmi, T. (2011). Algorithm and architecture co-design of hardware-oriented, modified diamond search for fast motion estimation in H.264/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 21(9), 1214–1227.
Lai, Y., et al. (2010). Hybrid parallel motion estimation architecture based on fast top-winners search algorithm. IEEE Transactions on Consumer Electronics, 56(3), 1837–1842.