Pipelining and transposing heterogeneous array designs
Journal of VLSI signal processing systems for signal, image and video technology - Tập 5 - Trang 7-20 - 1993
Tóm tắt
This paper describes a scheme for representing heterogeneous array circuits, in particular those which have been optimized by pipelining or by transposition. Equations for correctness-preserving transformations of these parametric representations are presented. The method is illustrated on developing novel pipelined designs for parallel division. It is estimated that, for a field-programmable gate array implementation, the speed of an integer divider can be doubled at the expense of a 50 percent increase in area.
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