Performance evaluation of mesh-based NoCs: Implementation of a new architecture and routing algorithm

S. Kumar, A. Jantsch, J. P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani. A network on chip architecture and design methodology. In Proceedings of IEEE Computer Society Annual Symposium on VLSI, IEEE, Pittsburgh, USA, pp. 105–112, 2002.

M. Millberg, E. Nilsson, R. Thid, S. Kumar, A. Jantsch. The Nostrum backbone-a communication protocol stack for networks on chip. In Proceedings of the 17th International Conference on VLSI Design, IEEE, pp. 693–696, 2004.

L. Benini, G. D. Micheli. Powering networks on chips: Energy-efficient and reliable interconnect design for SoCs. In Proceedings of the 14th International Symposium on Systems Synthesis, pp. 33–38, 2001.

L. Benini, G. D. Micheli. Networks on chips: A new SoC paradigm. IEEE Computer, vol. 35, no. 1, pp. 70–78, 2002.

P. Guerrier, A. Greiner. A generic architecture for on-chip packet-switched interconnections. In Proceedings of Design Automation and Test in Europe Conference and Exhibition, IEEE, Paris, France, pp. 250–256, 2000.

E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny. Cost considerations in network on chip. Integration, The VLSI Journal, no. 38, no. 1, pp. 19–42, 2004.

C. A. Zeferino, M. E. Kreutz, L. Carro, A. A. Susin. A study on communication issues for systems-on-chip. In Proceedings of the 15th Symposium on Integrated Circuits and Systems Design, IEEE, pp. 121–126, 2002.

E. Rijpkema, K. Goossens, A. Radulescu, J. Dielissen, J. van Meerbergen, P. Wielage, E. Waterlander. Tradeoffs in the design of a router with both guaranteed and best-effort services for networks on chip. In Proceedings of Design, Automation and Test in Europe Conference and Exhibition, IEEE, Munich, Germany, pp. 350–355, 2003.

E. Rijpkema, K. Goossens, P. Wielage. A router architecture for networks on silicon. In Proceedings of the 2nd Workshop on Embedded Systems, pp. 181–188, 2001.

B. S. Feero, P. P. Pande. Networks-on-chip in a threedimensional environment: A performance evaluation. IEEE Transactions on Computers, vol. 58, no. 1, pp. 32–45, 2009.

Noxim: Network-on-chip simulator, [Online], Available: http://sourceforge.net/projects/noxim , November 26, 2011.

L. Jain, B. M. Al-Hashimi, M. S. Gaur, V. Laxmi, A. Narayanan. NIRGAM: A simulator for NoC interconnect routing and application modeling. In Proceedings of the Friday Workshop on Diagnostic Services in Network-on-Chips, Design, Automation and Test in Europe Conference, France, 2007. [Online], Available: http://www.date-conference.com/files/file/10-ubooth/ub-1.4-p04.pdf , November 26, 2011.

D. A. Patterson, J. L. Hennessy. Computer Architecture: A Quantitative Approach, San Francisco, USA: Morgan Kaufmann Publishers, pp. 760, 1996.

F. Cen, T. Xing, K. T. Wu. Real-time performance evaluation of line topology switched ethernet. International Journal of Automation and Computing, vol. 5, no. 4, pp. 376–380, 2008.

P. Mohapatra. Wormhole routing techniques for directly connected multicomputer systems. ACM Computing Surveys, vol. 30, no. 3, pp. 374–410, 1998.

W. J. Dally, C. L. Seitz. The torus routing chip. Distributed Computing, vol. 1, no. 4, pp. 187–196, 1986.

Y. Wu, G. Min, M. Ould-Khaoua, H. Yin. An analytical model for torus networks in the presence of batch message arrivals with hot-spot destinations. International Journal of Automation and Computing, vol. 6, no. 1, pp. 38–47, 2009.

L. M. Ni, P. K. McKinley. A survey of wormhole routing techniques in direct networks. IEEE Computer, vol. 26, no. 2, pp. 62–76, 1993.

J. Duato, S. Yalamanchilli, L. M. Ni. Interconnection Networks: An Engineering Approach, San Francisco, USA: Morgan Kaufmann Publishers, 2002.

G. Ascia, V. Catania, M. Palesi, D. Patti. Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Transactions on Computers, vol. 57, no. 6, pp. 809–820, 2008.

D. Frazzetta, G. Dimartino, M. Palesi, S. Kumar, V. Catania. Efficient application specific routing algorithms for NoC systems utilizing partially faulty links. In Proceedings of the 11th EUROMICRO Conference on Digital System Design, Architectures, Methods and Tools, IEEE, Parma, Italy, pp. 18–25, 2008.

R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A communication-aware topological mapping technique for NoCs. In Proceedings of International Conference on Parallel and Distributed Computing, ACM, pp. 910–919, 2008.

M. Palesi, G. Longo, S. Signorino, S. Kumar, R. Holsmark, V. Catania. Design of bandwidth aware and congestion avoiding efficient routing algorithms for networks-on-chip platforms. In Proceedings of IEEE International Symposium on Networks-on-Chip, IEEE, Newcastle upon Tyne, UK, pp. 97–106, 2008.

G. Longo, S. Signorino, M. Palesi, S. Kumar, R. Holsmark, V. Catania. Bandwidth aware routing algorithms for networks-on-chip. In Proceedings of the 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, 2008, [Online], Available: http://www.diit.unict.it/users/mpalesi/DOWNLOAD/inaocmc08.pdf , November 26, 2011.

R. Tornero, J. M. Orduna, M. Palesi, J. Duato. A communication-aware task mapping technique for NoCs. In Proceedings of the 2nd Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, MENDELEY, 2008.

M. Palesi, S. Kumar, R. Holsmark, V. Catania. Exploiting communication concurrency for efficient deadlock free routing in reconfigurable NoC platforms. In Proceedings of IEEE International Parallel and Distributed Processing Symposium, IEEE, Long Beach, USA, pp. 1–8, 2007.

G. Ascia, V. Catania, M. Palesi, D. Patti. Neighbors-onpath: A new selection strategy for on-chip networks. In Proceedings of the 4th IEEE Workshop on Embedded Systems for Real Time Multimedia, IEEE, Seoul, Korea, pp. 79–84, 2006.

M. Palesi, R. Holsmark, S. Kumar, V. Catania. A methodology for design of application specific deadlock-free routing algorithms for NoC systems. In Proceedings of International Conference on Hardware-Software Codesign and System Synthesis, IEEE, Seoul, Korea, pp. 142–147, 2006.

M. Palesi, S. Kumar, R. Holsmark. A method for router table compression for application specific routing in mesh topology NoC architectures. In Proceedings of SAMOS VI Workshop: Embedded Computer Systems: Architectures, Modeling, and Simulation, pp. 373–384, 2006.

G. Ascia, V. Catania, M. Palesi, D. Patti. A New Selection Policy for Adaptive Routing in Network on Chip. In Proceedings of International Conference on Electronics, Hardware, Wireless and Optical Communications, ACM, pp. 94–99, 2006.

P. P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh. Performance evaluation and design trade-offs for networkonchip interconnect architectures. IEEE Transactions on Computers, vol. 54, no. 8, pp. 1025–1040, 2005.

Network topology, [Online], Available: http://en.wikipedia.org/wiki/Tree and hypertree networks #Tree, November 26, 2011.