Performance Analysis of Sub 10 nm Double Gate Circular MOSFET
Tóm tắt
In this work, TCAD based investigation of various Circular double gate MOSFET (CDGT) architectures have been carried for Low-Power(LP) & High- Performance (HP) applications at 10 nm gate length. Among all architectures, the optimum performance of CDGT is obtained by implementing both underlap & high – k dielectric material used as a gate stack. The hafnium -based CDGT architecture with 2 nm of underlap length provides good electrical properties, with an ION/IOFF ratio of ~1.55 × 107, a near-ideal subthreshold slope of ~66 mV/dec, and a reduced drain – induced barrier lowering of ~56 mV/V.
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