Partial product based improved reconfigurable FIR filter with control logic for automated guided vehicles on virtex-7 FPGA
Tóm tắt
5G-distinctive network control systems of the existing automated guided vehicles are likely to bring immense improvement in the performance using fifth generation of mobile communication (5G) technology. Recent days 5G communication systems are having requirement of FIR Filter having auto-adjustment of bandwidth. In the conventional finite impulse response filters, once the design is completed, we cannot change the frequency band. Thus, in auto adjustment frequency selective FIR filters to get desired bandwidth many filter coefficients are required. For implementation of field programmable gate array (FPGA). This generates a huge amount of slice. In this paper a control logic to choose different finite impulse response filters with set of coefficients based on clock signal, selects a finite impulse response filter resulting in frequency selectivity. The proposed design is to implement RFIR filter based on partial product having control logic to achieve better bandwidth needs with auto adjustment of frequencies. Filter order is used as 16. Area of overall designs is reduced by use of partial product in the FIR filter. The overall power consumed is 155 mw. Power consumption is reduced by 12.4%. Utilized area is reduced as compared to folded as well as unfolded direct form of FIR filter. Also, delay is reduced by 27.2% having value as 1.409 ns. The simulation outcomes of the design are validated through Xilinx ISE on virtex-7 FPGA.
Tài liệu tham khảo
Lee J-G, Lee D-Y, Myeong-Hoon O, Ko Y-W (2011) 472mhz Throughput asynchronous FIFO design on virtex-5 FPGA device. IEICE Electron Express. https://doi.org/10.1587/elex.8.676
Verma G, Kumar R, Khare V (2018) Regression based FPGA power estimation tool (FPE_Tool) for embedded multiplier block. Int J Inform Technol 11(2):1–4. https://doi.org/10.1007/s41870-018-0193-1
Karim E, Memon TD, Hussain I (2019) FPGA based on-line fault diagnostic of induction motors using electrical signature analysis. Int J Inform Technol 11:165–169
Motaqi A (2020) Energy-performance management in battery powered reconfigurable processors for standalone IoT systems. Int J Inform Technol 12:653–668
Saljooghi V, Bardizbanyan A, Själander M, Larsson-Edefors P (2012) Configurable RTL model for level-1 caches, NORCHIP, Copenhagen, Denmark, pp. 1–4. https://doi.org/10.1109/NORCHP.2012.6403112.
Singh AK (2019) A wireless networks flexible adoptive modulation and coding technique in advanced 4G LTE. Int J Inform Technol 11:55–66
Kiesel R, Henke L, Mann A, Renneberg F, Stich V, Schmitt RH (2022) Techno- economic evaluation of 5g technology for automated guided vehicles in production. Electronics 11(2):192. https://doi.org/10.3390/electronics11020192
Kalidindi Raju SN, Sudheer TK, Krishna VM (2021) Implementation of efficient reconfigurable FIR filter with control logic for 5G applications. Appl Soft Comput 25:10509–10518
Prabhat SC, Prashant K, Manish T, Amit D (2021) An efficient block-based architecture for reconfigurable FIR filter using partial product method. Circuits Syst Signal Process. https://doi.org/10.1007/s00034-021-01881-9(2021)
Sravanthi VN, Sudheer T (2020) Design and Performance Analysis of Rounding Approximate Multiplier for Signal Processing Applications. Smart Intelligent Computing and Applications. Volume 160. https://doi.org/10.1007/978-981-32-9690-9_41
Jia R, Yang H-G, Lin CY, Chen R, Wang X-G, Guo Z-H (2016) A computationally efficient reconfigurable FIR filter architecture based on coefficient occurrence probability. IEEE Trans Comput Aided Des Integer Circuits Syst 35(8):1297–1308
Bhagyalakshmi N, Rekha KR, Nataraj KR (2015) Design and implementation of DA-based reconfigurable FIR digital filter on FPGA. International Conference on Emerging Research in Electronics, Computer Science and Technology (ICERECT). 214–217.
Yeong-Jae O, Hanho L, Chong-Ho L (2006) A reconfigurable FIR filter design using dynamic partial reconfiguration, IEEE International Symposium on Circuits and Systems (ISCAS), Kos, Greece. https://doi.org/10.1109/ISCAS.2006.1693717.
Mahesh R, Vinod AP (2010) New reconfigurable architectures for implementing FIR filters with low complexity. IEEE Trans Comput-Aided Design Integr Circuits Syst 29(2):275–288
Mohanty BK, Meher PK (2016) A high-performance FIR filter architecture for fixed and reconfigurable applications. IEEE Trans Very Large Scale Integr (VLSI) Syst 24(2):444–452
Fransen K, Van Eekelen J, Pogromsky A, Boon MA, Adan IJ (2020) A dynamic path planning approach for dense, large, grid-based automated guided vehicle systems. Comput Oper Res 123:105046
Kiesel R, van Roessel J, Schmitt RH (2020) Quantification of economic potential of 5G for latency critical applications in production. Procedia Manuf 52:113–120
Hassan Aslam M, Umer Farooq M, Naeem Awais M, Bhatti K, Shehzad N (2016) Exploring the effect of LUT Size on the area and power consumption of a novel memristor-transistor hybrid FPGA architecture. Arab J Sci Eng 41:3035–3049